Menta, Codasip join RISC-V 3D neuromorphic AI project
The research wing of European RISC-V processor core developer Codasip and French embedded FPGA firm Menta have joined a project to build a 3D neuromorphic AI chip.
The €10m NimbleAI project aims to develop a neuromorphic sensing and processing 3D integrated AI chip by 2025
Codasip Labs, run by Codasip founder Karel Masařík, is to develop a RISC-V core using its Codasip Studio tool with instruction extensions customised for neuromorphic, or spiking, event-driven neural network as well as its CodAL architecture description language.
If everything goes according to plan, this will result in the creation of an integral neuromorphic architecture to efficiently run accurate and diverse computer vision algorithms for endpoint devices, says the company.
These are typically constrained in resources and area. Use cases include hand-held and battery-powered medical imaging devices, smart monitors for autonomous vehicles, or even wearable eye tracking glasses.
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The core will then be mapped on an eFPGA from Menta that can be updated regularly with new algorithms.
“Our technology has been built to be easily integrated with other partners technologies that all together are critical for low power ever evolving AI inference,” said Vincent Markus, CEO of Menta
Algorithms such as those used by AI evolve 4 times faster than the production rate of a chip so the ability to reprogramme the hardware of the chips allows them to be constantly adapted to these needs. Menta is currently the only industrialized European solution for embedded programmable logic and is involved in several European projects such as the EPI-SGA2 Project, the PROMISE Project and the new MOSAICs-LP Project.
Other members of the 19 strong project include French chip maker GrAI Matter Labs and EDA tool vendor MZ Technologies as well as CEA in France, imec in Belgium, the Universities of Manchester and Queen Mary in the UK and TU Eindhoven in the Netherlands.
The project expects to achieve 100x energy-efficiency improvement and 50x latency reduction through in-memory computing and the eFPGA as well as embedded ReRAM-based storage with 3D circuit layers using through silicon vias.
www.nimbleai.eu; www.codasip.com; www.menta-efpga.com
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