Mentor refines power prediction in complex SoC designs

Mentor refines power prediction in complex SoC designs

Technology News |
By eeNews Europe

The Veloce Power Application, mentor says, delivers a complete solution that enables a new comprehensive methodology for power, embodying accurate and early switching activity at the application level. Users can carry out early budgeting and tradeoff exploration at RTL; and analysis and sign off at the gate level. Real-time transfer of power switching activity, via a Dynamic Read Waveform API, to power analysis tools replaces current file-based activity transfer methodology – this feature employs close integration with third-party power analysis tools

Mentor Graphics’ starting point is that a new usage model for handheld and smart devices is driving a methodology shift in the way power is analysed; the company cites Qualcomm as having made a significant input into the desired feature list for this software. One primary driver in this shift is the fact that complex SoC designs are now verified using live applications that require booting the OS and running software applications on an emulator. It is more effective to use the power switching activity plot, generated during emulation, to pass real-time switching activity information to power analysis tools where potential power issues can be evaluated.

When this is done today, Mentor says, the default approach is to boot designs that are heavily software- or application-driven on the emulator, then generate output files of activity which can then be read by a downstream power analysis tool. Issues around this approach are that for meaningful application (or even OS) runs, files can be unmanageably large, and the analysis tools can take unacceptable time to read them – if reading them is even practical. In this release, Mentor provides a means of identifying power peaks in the SoC’s (or its constituent blocks’) demand, and writing out only the intervals that see the critical power peaks. Further, via an API, the data is copied directly to the downstream analysis tool, rather than via a file.

The file-based power analysis flow is replaced by a Dynamic Read Waveform API integration to power analysis tools. This enables accurate power calculation at the system level, better power exploration at RTL for power budgeting and tradeoffs as well as more accurate power analysis and sign-off at the gate level.

The result, Mentor says, is a significant boost in runtime and performance. The typical approach of running the emulator, creating the file, reading the file into the power analysis tool and running the power analysis tool is now, with this new approach, reduced to the emulator and power analysis runtimes. Mentor adds that early users have seen up to a 4.5X runtime performance improvement.

Mentor aims to make the flow independent of the generation of Veloce hardware that a user has; and agnostic as regards the power analysis tool employed. The first Veloce Power Application ecosystem partner is ANSYS with PowerArtist. “This collaboration addresses the challenges for designers of energy-efficient IP and SoC designs in various IoT verticals,” said Vic Kulkarni, Sr. vice president and general manager, RTL power business, at Apache division of ANSYS.

The Veloce Power Application integration with ANSYS PowerArtist is available to mutual customers on a limited basis. Full production release is scheduled for early Q4/CY 2015.


You can access a white paper giving more details of the approach here.



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