Mentor wins emulation role for Imagination Technologies’ IP verification
“The 800 M-gate Veloce Maximus helps improve our productivity for verification of our advanced IP cores and the Veloce co-modelling technology enabled us to reduce our regression times,” Mark Dunn, EVP, IMGworks SoC Design, Imagination Technologies, is quoted as saying.
According to Eric Selosse, vice president of the Mentor Emulation Division. “[Imagination has] shown us how better emulation technology helps their business through benefits such as better coverage of corner cases, increased co-model throughput, better debug, and low power verification.”
The Veloce 2 emulation platform allows high-performance simulation accelerations, virtualised emulation, and traditional in-circuit emulation of complex SoC designs. The Veloce 2 platform achieves these benefits through an emulation-on-chip architecture and associated software and hardware technologies, delivering fast compiles, full debug visibility, power aware and analysis tools, and advanced memory modelling. Protocol solutions provide off-the-shelf portfolios of easy-to-use verification IPs (VIPs), ICE applications (iSolve), and VirtuaLAB components that are an essential part of verifying both IP and SoC-based designs.
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