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Microchip starts 64bit PIC64 family with RISC-V

Microchip starts 64bit PIC64 family with RISC-V

Technology News |
By Nick Flaherty



Microchip has launched its first 64bit microprocessor line, starting with a multicore RISC-V cluster for its PIC64GX family.

The PIC64 GX1000 uses the existing RISC-V four core cluster with a fifth microcontroller as a system monitor from its PolarFire FPGA family launched back in 2019 and on the same process technology. But Microchip also plans versions with 64bit A-class ARM processor cores. The company is also qualifying a stand alone eight core 64bit RISC-V networking chip for space applications following the use of the FPGA in space systems.    

“We are ready to launch a line of 64bit MCUs and first out of the gate we have taken the multicore subsystem (MSS) and made a product out of it to extend into the non-FPGA world,” said Shakeel Peera, VP of strategy and business operations for the FPGA business unit at Microchip.

“What you will see is regular platforms and families for 64bit processors that are ISA agnostic, so there will be ARM as well,” he said. “With RISC-V we wanted a homogeneous core complex to minimise the number of transistors for asymmetric multi processing (AMP) to minimise static current and power.” The RISC-V cores were co-developed for PolarFire with SiFive using the U54 core with custom extensions and Microchip has added fixed function blocks for video, and imaging and video.

“This is the same 28nm process,” said Peera. “You choose a process based on the complexity you want and the 625MHz cluster frequency is lower MIPS in performance and the idea is to keep the wafer costs low.”

The GX1000 has a 2MB SRAM level two (L2) cache with a flexible design that can be allocated to the four core or uses as a shared memory. This impact son the core designs as this requires the branch prediction units of each core to be switched off.

This allows real time Linux to run on the monitor core and the four cores to run mainstream Linux, or the Zephyr RTOS on two cores and two cores running Linux. The peripherals are also partionable to specific cores, with up to four Gen2 PCIexpress links allocated to the management core. There is also a secure boot ROM to provide a root of trust and for key storage as well as two physically unclonable functions (PUF) for key provisioning 128bit entropy from the SRAM and the bus keeper.

A higher performance version, the GX1100, is planned for March 2025 with separate memory mapped machine learning acceleration block, H.264 video codec, DSI-2 interconnect  and 16 or 32 lines DDR4.

“As we go forwards we will have other versions for intelligent edge with real time processing and all require a series of single core, multicore processors with specific features.”

Microchip is also developing its own system on module (SoM) using the 64bit RISC-V processor.

The development tools are the key to the 64bit PIC64 line with both RISC-V and ARM cores, using VScode extensions extending down to 32bit, 16bit and even 8bit microcontrollers.

“There are 50,000 tool starts every day with MPlab, it has a very wide footprint so we want to use MPlab for starting the design,” he said. The company has 28 product lines from 24 business units.

The PIC64 MPUs are also supported by Linux4Microchip resources and Linux distributors such as Canonical Ubuntu OS, the Yocto Project and Buildroot with support for Zephyr RTOS and associated software stacks.

Microchip has also developed a Curiosity evaluation board for the GX1000, which can be used as a single board computer (SBC) with one cable with a pre-programmed web server to link to the git repo.

 In the 5000 quantities, the GX1000 RISC-V multicore PIC64 process will cost around $20.

www.microchip.com

 

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