MicroLEDs for long range terabit optical chip interconnect
Avicena has developed a parallel terabit optical interconnect for chip-to-chip links with a range of up to 10m.
The longer reach means the LightBundle optical interconnect technology targets distributed computing, processor-to-memory disaggregation, and other advanced computing applications.
The technology uses arrays of GaN high-speed micro-emitters from microLED display manufacturing ecosystem, and is fully compatible with high performance silicon ICs.
Because optical interconnects do not have these same power and reach limitations as SerDes copper links, they have long been the prime contender to replace electrical interconnects for inter-chip communications. However the optical technologies typically designed for networking applications have been impractical for inter-processor and processor-memory interconnects due to their low density, high power consumption, inability to tolerate the high operating temperature of ASICs, and high cost.
“All of this is changing with the recent advances in optical emitter technology driven by advances in the display industry,” says Bardia Pezeshki, founder and CEO of Avicena. “We have developed very high-performance optical transmitters based on emitter technology from the display industry. These innovative devices would have been impractical just a few years ago. Our optimized devices and materials support 10Gbps links per lane over -40°C to +150°C temperature with excellent reliability. We refer to our new optical sources as Cavity-Reinforced Optical Micro-Emitters or CROMEs. We connect CROME arrays with CMOS compatible PDs using multi-core fiber bundles to create massively parallel interconnects with 1000s of parallel lanes over a reach of up to 10m.”
Avicena this week demonstrated an array of 200 CROME devices with a pitch of 30μm coupled to an array of PDs with a multi-core imaging fibre. Individual lanes show data rates up to 10Gbit/s over the full temperature range of -40°C to 150°C. This extrapolates to an aggregate link bandwidth of 2Tbit/s for 200 lanes with a bandwidth density of 10Tbit/mm2 with power efficiency of 0.1pJ/bit.
The parallel nature of the LightBundle technology is also suited to parallel chiplet interfaces such as AIB, HBI, and BoW, and can also be used to extend the reach of standard compute interconnects like PCIe, Nvidia’s NVLink, and multi-channel G/DDR memory links with low power and low latency.
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