Micron collaborates with Broadcom to improve DRAM timing and speed of operation
14.00
tFAW refers to a DDR3 timing parameter that restricts data throughput in server, storage and networking applications and can compromise bandwidth by 15 to 35 percent. With every new DRAM generation, the access granularity is becoming double, causing some timing parameters like tRDD and tFAW to restrict data throughput. This creates challenges for high-performance applications because no more than four bank activate commands can be issued in any given tFAW period.
The Micron solution validated by Broadcom reduces the tFAW value from 35ns to 30ns for a 2KB page size, DDR3-2133, improving operations per second by 18 percent. This performance increase is especially critical for complex packet processing functions, such as highly scalable IPv4 and IPv6 lookups used in service provider networking applications. The four activate window solution enables Broadcom’s BCM88030 200 Gb/s NPU to achieve extremely scalable L2, IPv4 and IPv6 lookup capacities at wire speed performance using Micron’s DDR3 memory.
Micron’s 2Gb and 4Gb DDR3 with the reduced tFAW timing specification are available in volume production now.
Visit Micron Technology at www.micron.com
Normal
0
false
false
false
EN-GB
X-NONE
X-NONE
/* Style Definitions */
table.MsoNormalTable
{mso-style-name:”Table Normal”;
mso-tstyle-rowband-size:0;
mso-tstyle-colband-size:0;
mso-style-noshow:yes;
mso-style-priority:99;
mso-style-parent:””;
mso-padding-alt:0cm 5.4pt 0cm 5.4pt;
mso-para-margin:0cm;
mso-para-margin-bottom:.0001pt;
mso-pagination:widow-orphan;
font-size:10.0pt;
font-family:”Calibri”,”sans-serif”;}
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
