Microprocessor comes with vision-optimized AI accelerator

Microprocessor comes with vision-optimized AI accelerator

New Products |
By Julien Happich

The first product in the series, the RZ/V2M, is designed to deliver a combination of real-time AI inference and industry-leading power efficiency in embedded devices. The RZ/V2M leverages the DRP-AI’s excellent power efficiency to draw as little as 4W (typ.). This eliminates the need for heat sinks and cooling fans, greatly simplifying heat dissipation measures. This enables RZ/V2M to be used in compact devices or help to minimize equipment sizes, expanding the opportunities to incorporate AI in embedded devices. It also helps to reduce bill-of-materials (BOM) costs.

In addition to the DRP-AI, the RZ/V2M features an imaging signal processor (ISP) capable of processing high-resolution 4K pixels at 30 frames per second. The ISP employs high dynamic range (HDR) functionality capable of handling images with large differences between brightness and darkness, noise reduction functionality, and distortion correction functionality to substantially boost precision in AI recognition. This ensures the ability to produce clear images regardless of factors such as the weather, the time of day, and the installation location.

The DRP-AI vision-optimized AI accelerator is an intellectual property (IP) evolved from the DRP built into the RZ/A2M, designed for tasks such as reading 2D barcodes and iris recognition. To magnify operation processing capabilities, the DRP functionality is combined with an AI-MAC (multiply and accumulate) circuit, making it ideal for applications utilizing AI inference. The new IP core is capable of AI processing with approximately 10 times the power efficiency of the DRP, achieving the 1 TOPS/W class. In addition, since the DRP can dynamically change the configuration of its operation circuits every clock cycle, the DRP-AI adds the ability to flexibly support ever-evolving and advancing AI algorithms. Renesas also plans to offer the DRP-AI Translator, a tool deciated for DRP-AI based development that simplifies the implementation of user’s learned AI models into embedded devices. Delivered in a 15×15mm FCBGA package, the CPU is built around dual Arm Cortex-A53 cores with an operating frequency of 1 GHz. Samples are available now for early adopters, and mass production is scheduled to start in December 2020.

Renesas –

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