Microsemi adds full IDE to RISC-V package on programmables

Microsemi adds full IDE to RISC-V package on programmables

Technology News |
By Graham Prophet

SoftConsole version 5.1 is an IDE for designs utilizing RISC-V open instruction set architectures (ISAs) such as RV32I. SoftConsole, Microsemi offers the free software development environment enabling rapid production of C and C++ programming language designs for its field programmable gate arrays (FPGAs): the company highlights its open architecture, low power and development capabilities using RISC-V soft central processing unit (CPU) cores.


“With the majority of Microsemi FPGA designers utilizing a Windows platform for their development efforts, SoftConsole v5.1 not only supports our RISC-V soft CPU cores to enable designs with our highly secure and reliable FPGAs, but it can also be used for any RV32I standard ISA extensions,” said Tim Morin, director of marketing at Microsemi. “This product release broadens the RISC-V ecosystem for those developing on Windows machines, and leverages our leadership position as we continue investing in this architecture to provide customers dependable, long-term roadmap support.”


Microsemi’s SoftConsole v5.1, a GNU compiler collection (GCC), now supports both Windows and Linux for RISC-V designs and can be used for RV32I implementations including extensions to the baseline RV32I architecture such as M,A,F,D,G and C. Offering low power and an open architecture, it supports Microsemi’s PolarFire, RTG4, SmartFusion2 and IGLOO2 (block diagram) FPGA-based RISC-V soft CPUs as well as the HiFive1 Arduino kit from SiFive, a fabless semiconductor company that produces computer chips based on the RISC-V ISA. SoftConsole v5.1 is suitable for developing a wide variety of applications within the aerospace and defence, communications, data center and industrial markets.

RISC-V, an ISA which is now a standard open architecture under the governance of the RISC-V Foundation, offers numerous benefits, including enabling the open source community to test and improve cores at a faster pace than closed ISAs. As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures. Portability is another benefit of the technology. For example, designers can begin development with Microsemi’s RISC-V core in its FPGAs and then move to an application-specific integrated circuit (ASIC) royalty-free.


As a free software development environment supporting development of C and C++ executables for Microsemi’s FPGAs using RISC-V soft CPU cores, SoftConsole v5.1 provides a flexible graphical interface for managing embedded software development projects. Users can develop and debug software programs and implement them in Microsemi FPGAs, with a fully integrated debugger offering access to memory contents, registers and single-step execution. SoftConsole also enables users to configure project settings and organize files, provides simultaneous access to multiple tool windows, and delivers the ability to switch editing and debug views. Libero SoC, Microsemi’s comprehensive suite of FPGA design tools, includes the Firmware Catalog to export firmware for soft CPU FPGA designs which can be imported into SoftConsole.


Linley Gwennap, principal analyst at The Linley Group, adds, “RISC-V is a modern take on the classic RISC instruction set, providing a clean and extensible approach suitable for a broad range of microprocessor implementations. More significantly, the open source, royalty-free RISC-V instruction set creates a new business model for CPU designers,” said Gwennap. “This combination has generated sizable industry interest in RISC-V, which will lead to several commercial deployments this year and beyond.”


Microsemi’s SoftConsole v5.1;



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