Mid-range, flash-based FPGAs offer 500 LEs, 12.7G SerDes

Mid-range, flash-based FPGAs offer 500 LEs, 12.7G SerDes

New Products |
By Graham Prophet

The programmables offer up to 500k logic elements, 12.7G transceivers at up to 50% lower power than competing mid-range FPGAs, and also feature optimised security and reliability. Microsemi aims the product familyfor a range of applications within wireline access networks and cellular infrastructure, defence and commercial aviation markets, as well as industry 4.0 which includes the industrial automation and Internet of Things (IoT) markets.


Bruce Weyer, vice president and business unit manager at Microsemi, says, “… a non-volatile FPGA, with all its known benefits, provides tangible power and cost benefits over SRAM FPGAs that feature 10 Gpbs transceivers—thus delivering differentiation … [and] simultaneously filling a void in the market.” This chart from Microsemi’s presentation shows (in various shades of blue) the sectors of the programmables market that it seeks to address.

For the communications infrastructure market, Microsemi presents these devices as providing cost-effective bandwidth processing capabilities for the increasing number of converged 10 Gpbs ports with the lowest power footprint. The new FPGA product family also contains features to address the market’s concerns over cyber security threats as well as reliability concerns that face deep submicron SRAM-based FPGAs as they relate to single event upsets (SEUs) in their configuration memory. The company says that a radiation-induced event that could ‘flip’ a bit in the configuration SRAM of a competitive part would leave its non-volatile configuration memory unaffected. Additional features to aid with reliability include built-in single error correction and double error detection (SECDED) as well as memory interleaving on large static random access memory (LSRAMs), and system controller suspend mode for safety critical design

Applications sought in the communications market include wireline access, network edge, metro (1-40G); wireless heterogeneous networks, wireless backhaul, smart optical modules and video broadcasting. The devices are also suited to applications within the defence and aerospace market, such as encryption and root of trust, secure wireless communications, radar and electronic warfare (EW), aircraft networking, actuation and control. Suitable applications for the FPGAs within the industrial market include process control and automation, machine vision processing and analytics, programmable logic controllers, industrial networking, and video and image processing.


In collaboration with Silicon Creations, Microsemi has developed a 12.7 Gbps transceiver fully optimized to be area efficient and low power, resulting in total power of less than 90 mW at 10 Gbps. With low device static power of 25 mW at 100k logic elements (LEs), zero inrush current and its Flash*Freeze mode for standby power of 130 mW at 25C, PolarFire devices are up to 50% lower power than competing FPGAs for the same application. Microsemi provides designers with a power estimator to analyze power consumption of their designs.


PolarFire FPGAs offer Cryptography Research Incorporated (CRI) patented differential power analysis (DPA) bitstream protection, integrated physically unclonable function (PUF), 56 kB of secure embedded non-volatile memory (eNVM), built-in tamper detectors and countermeasures, true random number generators, integrated Athena TeraFire EXP5200B Crypto Co-processors (Suite B capable) and a CRI DPA countermeasures pass-through license.


The devices’ cost-optimized architecture uses 28 nm Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) non-volatile process technology on standard CMOS. PolarFire FPGAs also incorporate transceiver performance optimized for 12.7 Gbps enabling smaller size and lowest power, hardened I/O gearing logic for double date rate (DDR) memory and low-voltage differential signalling (LVDS), high performance security IP and the industry’s only low cost mid-range device with clock and data recovery (CDR) capable 1.6 Gbps I/Os.


Microsemi’s Libero SoC design tools have been extended to PolarFire FPGAs. The suite includes a complete design flow with Synopsys Synplify Pro synthesis and Mentor Graphics ModelSim Pro mixed-language simulation with best-in-class constraints management, and Microsemi’s differentiated FPGA debugging suite, SmartDebug. Popular IP solutions for 1G Ethernet, 10G Ethernet, JESD204B, DDR memory interfaces, AXI4 interconnect IPs and others are available for use with PolarFire devices. The series also features SmartDebug – Live Probe: without any overhead or re-compilation, any two points within the device can be brought out to display waveforms on an oscilloscope. SerDes debug, displaying a true eye diagram of a high-speed serial waveform, is also provided. A high performance evaluation kit will be available in the second quarter of 2017, with a lower-cost version with a selection of popular interfaces, in Q3.


Device features include;

– Serial connectivity with built-in multi-gigabit multi-protocol transceivers from 250 Mbps to 12.7 Gbps

– Up to 481,000 logic elements consisting of a four-input look-up table (LUT) with a fracture-able D-type flip-flop

– Up to 33 MB of RAM

– Up to 1480 18 x 18 multiply accumulate blocks (MACs) with hardened pre-adders

– Integrated dual PCIe for up to x4 Gen2 endpoint (EP) and root port (RP) designs

– High-speed I/O (HSIO) supporting up to 1600 Mbps DDR4, 1333 Mbps DDR3L and 1333 Mbps LPDDR3/DDR3 memories with integrated I/O gearing

– General purpose I/O (GPIO) supporting 3.3 volts (V), built-in clock and data recovery (CDR) for serial Gigabit Ethernet (SGMII), 1067 Mbps DDR3 and 1600 Mbps low-voltage differential signaling (LVDS) I/O speed with integrated I/O gearing logic

PolarFire is shipping to early access customers now and samples for general availability will be offered in the second quarter of 2017.




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