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MIPI DSI Host and peripheral IP cores in 65nm and 40nm

MIPI DSI Host and peripheral IP cores in 65nm and 40nm

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By eeNews Europe



Part of the company’s FlexIP core library, these DSI IP solutions can be used in tandem with HDL Design House MIPI D-PHY IP core, available in advanced technology nodes and with silicon proven status. The MIPI DSI Host IP core (HIP 3500) is a configurable digital core, compliant with the MIPI Alliance DSI specification, providing a high-speed serial interface between an application processor and MIPI DSI compliant display. It supports MIPI DSI protocol version 1.1, MIPI DCS version 1.0, MIPI DBI version 2.0, MIPI DPI version 2.0, MIPI D-PHY version 1.0. The HIP 3500 is fully compliant with AMBA AHB Version 2.0 Compliant Slave Interface. HDL Design House HIP 3500 can be configured to handle 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 bits (a.k.a. RGB565, RGB666, RGB888).

The MIPI DSI Periph (Device) IP core (HIP 3510) receives pixel data and commands from host processor through D-PHY interface and sends data to DPI or DBI interfaces. HIP 3510 is a highly configurable digital IP core, supporting 1 to 4 data lanes. The HIP 3510 is fully compliant to MIPI Alliance’s DSI, MIPI DBI version 2.0, DPI version 2.0, and DCS standards, as well as to AMBA’s AHB specification. HDL Design House HIP 3500 can be configured to handle 1 to 4 data lanes and supports image resolutions: QQVGA, QVGA, VGA, WVGA, XVGA, Full-HD and pixel formats: RGB 16, 18, 24 bits, (a.k.a. RGB565, RGB666, RGB888). It supports both command and video modes of operation. These MIPI DSI solutions are available now, along with the silicon-proven MIPI D-PHY IP core in 65nm and 40nm.

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