MIPS adds Virtualization and SIMD in latest core architecture release
Release 5 of the ISA adds modules for single instruction, multiple data (SIMD) and scalable virtualization as well as Enhanced Virtual Addressing (EVA) technology to extend the available memory space for large modern workloads.
The Scalable Virtualization (VZ) module provides secure hardware virtualization across a range of applications from microcontrollers to high-end enterprise, adding new instructions for a hardware-assisted hypervisor and registers for individual user states to support multiple operating systems securely and separately from the root privileges (see figure above for the MIPS ASE ‘onion’ model of virtualization).
The development of new secure hypervisors is currently underway. “Virtualization only changes the instruction sets by adding a few instructions to manage the Guest Context,” said a spokesperson for MIPS. “These instructions are never used by regular applications (this would be a security hole) but ONLY used by the hypervisor. The hypervisor would access these new instructions though the assembler, not the compiler.”
Another addition, the MIPS SIMD architecture (MSA) module, allows more efficient parallel processing of vector operations for consumer electronics such as mobile and home entertainment devices, as well as higher throughput data movement for scientific/high-performance computing and data mining. The MSA module will add a number of new instructions to the MIPS architecture and is initially 128bits wide, although it can be extended further, says said Mark Throndson, director of product marketing at MIPS.
Popular multi-threading and DSP extensions have also been integrated as modules within the base MIPS architecture rather than as application specific extensions (ASE) that are licensed separately and the Enhanced Virtual Addressing (EVA) that was recently added to the MIPS architecture with the proAptiv and interAptiv core families earlier in the year.
Key features of the MIPS architecture R5 specification are available for licensing now and several MIPS licensees already have products in development. These features are expected to be added to MIPS processors in the coming year.
“Broadcom is pleased to continue our close working relationship with MIPS to develop the latest flexible, scalable architecture for hardware virtualization, as well as to continue leading the market with highly innovative multicore processors,” said Ron Jankov, Senior Vice President & General Manager for Processors and Wireless Infrastructure at architecture licensee Broadcom. “Our advanced MIPS64-based communications processors combine quad-issue, multithreaded instruction pipelines with up to 128 NXCPU processing units for greater performance for enterprise, data center and service provider networks.”
Another architecture licensee, Cavium, supported the new release. “As a long-time licensee of the MIPS64 architecture, we are pleased to continue to bring to market new and innovative products based on MIPS, including our new OCTEON Fusion base station-on-a-chip processors, and our next generations of our OCTEON III multi-core processors,” said YJ Kim, General Manager of the Infrastructure Processor Group. “The flexibility and scalability of the MIPS architecture along with our architecture license enables us to continue to push the envelope of performance and features of our advanced processors to increasingly higher levels.”
Low cost chip designer Ingenic Semiconductor is also interested in the SIMD extensions for consumer applications. “The efficient and scalable MIPS architecture enables us to build processors that are high performance and cost effective, with ultra low power consumption. We are pleased to see continued evolution of the MIPS architecture, with the addition of innovative new instructions that support the next generation of products. In particular, we believe that SIMD functionality will be increasingly important to support media-rich applications in mobile products,” said Qiang Liu, CEO at Ingenic.
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