MIPS expands CPU portfolio with new 32-bit and 64-bit offerings
The MIPS P6600 is the next evolution of the MIPS P-class family, building on the 32-bit P5600 CPU, and paving the way to future generations of higher performance 64-bit MIPS processors. The P6600 is the most balanced mainstream high-performance CPU choice, enabling powerful multicore 64-bit SoCs with optimal area efficiency for applications in segments including mobile, home entertainment, networking, automotive and more.
All based on the MIPS Release 6 (r6) architecture, the products extend the range of Imagination’s solutions in the high-volume mainstream CPU IP market. The MIPS P6600 is a high-performance 64-bit MIPS Warrior CPU based on a 16-stage multi-issue Out of Order (OoO) pipeline implementation, delivering outstanding computational throughput and area efficiency. It features integrated compiler-friendly 128-bit MIPS SIMD Architecture (MSA) support for efficient parallel processing of vector operations in multimedia applications. Other features include sophisticated branch prediction with fully associative Level 1 BTB (branch target buffer) and an improved Level 2 cache sub-system. It supports full hardware virtualization and Imagination’s OmniShield technologies for enhanced security and reliability in a wide range of applications.
Both the MIPS M6200 MCU & M6250 MPU are compact 32-bit CPUs based on a 6-stage pipeline implementation, enabling 30% higher frequencies versus the MIPS microAptiv CPU for similar implementations. They come with integrated DSP and SIMD functionality to address signal processing requirements of such applications as industrial/motor control, voice processing and more. They support the microMIPS r6 Instruction Set Architecture (ISA) for superior code compression and reduced memory footprint, but also data integrity features such as ECC and parity protection.
The M6200 MCU includes a memory controller for tightly coupled 64-bit instruction/Data SRAM, a memory protection unit enables program/data security. The M6250 MPU includes a memory controller for Instruction/Data L1 cache and optional tightly coupled ScratchPad RAMs (SPRAMs). A Memory Management Unit (MMU) supports virtual memory, enabling full support for Linux and other high level operating systems. It also offers 40-bit eXtended Physical Addressing (XPA) support and comes with an AMBA AXI3 Bus Interface Unit.
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