The I7200 core delivers 50% higher performance with only a 20% increase in size over the previous generation from MIPS. The new core is a member of the MIPS 32-bit I-Class family of processor cores. It is built on MIPS’ multi-threading technology, which delivers both higher levels of performance efficiently and very low latency response to high priority events in real-time embedded systems. To get those levels of performance the I7200 provides multi-threading with thread prioritization and zero cycle context switching, configurable memory management and tightly coupled, fast-access, deterministic ScratchPad RAMs.
The I7200 is also the first MIPS core to use the nanoMIPS ISA, which delivers a smaller code size. nanoMIPS is a variable instruction length ISA consisting of 16/32/48-bit instructions and other optimisations that deliver performance in a compact code size. By using an equivalent compiler and compile flags, the code size is up to 10% smaller than alternative cores competing in similar applications.