Mipsology FPGA machine learning port for the data centre
European machine learning and AI software developer Mipsology has signed a deal to use its Zebra neural network accelerating software in the latest build of Xilinx’s Alveo U50 data centre accelerator card.
The Alveo U50 is the industry’s first low profile adaptable accelerator with PCIe Gen 4 support. The Zebra tool allows machine learning frameworks to be quickly and easily moved onto an FPGA as an inference engine which with the smaller profile of the Alveo card allows more inference performance over CPUs and GPUs.
“When we started Mipsology we looked at who would use it, so we didn’t change the framework, we didn’t change the training, we didn’t change the tools, so this meant we are 99.5% transparent,” said Ludo Larzul, CEO and founder of Mipsology and the former CEO of French emulator company EVE. “We have developed all the layers up to the machine learning framework so with a single Linux command in the framework we catch the call that is supposed to go to the GPU and it goes to our stack and goes to our driver on a FPGA board. There is no API because all we do is the framework,” he said.
The key for data centre users is simplicity and performance he says. Zebra is designed so that no knowledge of hardware or software is necessary, just the machine learning framework.
“We do everything in the INT8 [8bit integer format] for performance,” he said. “Five years ago we did FP32 [32bit floating point, often used for training] but we dropped that as everyone was moving to INT16 so we reprogrammed the FPGA to INT16 – then we introduced our own quantisation to INT8. We can take the FP32 framework such as Resnet152 which might take 10 to 15 minutes and we keep the accuracy, within 1% of difference.”
“The level of acceleration that Zebra brings to our Alveo cards puts CPU and GPU accelerators to shame,” said Ramine Roane, Xilinx’s Vice President of marketing. “Combined with Zebra, Alveo U50 meets the flexibility and performance needs of AI workloads and offers high throughput and low latency performance advantages to any deployment.”
This is the latest in a series of Zebra-enhanced Xilinx boards that enable inference acceleration for a wide variety of sophisticated AI applications. Others include the Alveo U200 and Alveo U250 boards.
“Every year we double the performance on the same FPGA and we can get more INT8 performance out of the device than the physical resources. It’s what Xilinx calls an overlay. We do the RTL in house for the hardware and we do the C++ for the libraries,” said Larzul.
“The Zebra accelerator architecture is extremely scalable so with the exact same RTL we can target a small FPGA or large FPGA with less than 10 parameters – because we know the structures of the FPGA. We tweak the parameters for performance, the number of users and the amount of DDR memory,” he said.
Mipsology is at www.mipsology.com
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