MIT spinout to build true 3D chips with 2D materials
Researchers at MIT in the US have developed a technique for building true monolithic 3D chips using 2D materials.
The research, backed by Samsung and the US Air Force, is being spun out into a new company called Future Semiconductor 2D materials (FS2) as the technique can be used for both logic and memory.
Rather than using the mainstream through-silicon-via (TSV) technique, the team at MIT have been able to place single crystal layers of 2D transition metal dichalcogenide (TMD materials on amorphous and polycrystalline surfaces at temperatures low enough to preserve the underlying electronic components.
This was used to create a seamless monolithic integration of vertical single-crystalline logic transistor arrays that is compatible with CMOS devices and process technology.
“This opens up enormous potential for the semiconductor industry, allowing chips to be stacked without traditional limitations,” says Jeehwan Kim, associate professor of mechanical engineering at MIT. “This could lead to orders-of-magnitude improvements in computing power for applications in AI, logic, and memory.”
In their previous work, the team grew TMDs on silicon wafers with amorphous coatings, but needed temperatures over 900 deg C which is too hot for existing CMOS.
“You have to grow this single-crystalline material below 400 Celsius, otherwise the underlying circuitry is completely cooked and ruined,” said Kim. “So, our homework was, we had to do a similar technique at temperatures lower than 400 Celsius. If we could do that, the impact would be substantial.”
The team looked to grow single-crystalline TMDs on a silicon wafer that already has been fabricated with transistor circuitry. They first covered the circuitry with a mask of silicon dioxide, and deposited “seeds” of TMD at the edges of each of the mask’s pockets and found that these edge seeds grew into single-crystalline material at temperatures as low as 380 degrees Celsius, compared to seeds that started growing in the centre, away from the edges of each pocket, which required higher temperatures to form single-crystalline material.
This was used to build a structure with alternating layers of molybdenum disulfide for the n-type transistors and tungsten diselenide for the p-type transistors without the need for any intermediate silicon layers. This could double the density of CMOS elements in 3D chips says Kim.
“A product realized by our technique is not only a 3D logic chip but also 3D memory and their combinations,” he said. “With our growth-based monolithic 3D method, you could grow tens to hundreds of logic and memory layers, right on top of each other, and they would be able to communicate very well.”
“Conventional 3D chips have been fabricated with silicon wafers in-between, by drilling holes through the wafer — a process which limits the number of stacked layers, vertical alignment resolution, and yields,” adds researcher Kiseok Kim. “Our growth-based method addresses all of those issues at once.”
“We so far show a concept at a small-scale device arrays,” he says. “The next step is scaling up to show professional AI chip operation.” This is the plan for 3D chips at FS2.
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