MIT, TI tip 28-nm applications processor
In a paper, TI and MIT will present research detailing design methodologies for a 28-nm mobile applications processor with ultra-low power. The paper-entitled ”A 28 nm 0.6 V Low Power Digital Signal Processor (DSP) for Mobile Applications”-demonstrates that a DSP is capable of scaling from a high-performance mode at 1.0 V down to an ultra-low power (ULP) mode at 0.6 V.
This DSP is one of the first low-voltage, 28-nm designs for the mobile device market. At present, TI, Nvidia, Qualcomm and others are battling each other in the applications processor market in the mobile space. Each company is also racing each other to ship 28-nm designs.
TI’s 28-nm device is based on a 4-issue, 32-register version of the TMS320C64x VLIW DSP. The system-on-a-chip (SoC) includes 32 kB L1 and 128 kB L2 caches, as well as I2S, SPI, UART, multimediacard and external memory interfaces.
”The design incorporates over 600k instances of custom low-voltage logic cells and 43 instances (1.6 Mb) of 6T SRAM,” according to the paper from TI and MIT.
”Utilizing ultra-low-voltage (ULV) optimized standard-cell libraries and 6T SRAM macros, and demonstrating a new statistical static timing analysis (SSTA) methology, the SoC scales as designed from high performance at 1.0 V down to ultra-low-power at 0.6 V.”
The device is operational at 587-MHz at 1.0V (113 mW). At 0.5 V, the maximum frequency is 43.4-MHz.
The chip is made using 193-nm immersion lithography with double patterning techniques. It also makes use of a dual-gate poly/SiON gate stack. It also utilizes ”epitaxial S/D SiGe for pMOS performance enhancement,” according to the paper. ”Typical strain techniques are also used for nMOS performance enhancement.”
In the ISSCC paper, MIT and TI are expected to provide more details on Tuesday (February 22).
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