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Mixed-language verification platform for waveform-based HDL debugging

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By eeNews Europe

Riviera-PRO 2013.02 includes a Plot window supporting four different plot types to enable more efficient visualization of large data sets, as well as the ability to visualize and analyze relations between any objects within a design with no additional programming required.

The traditional approach to analyzing objects in an HDL design, based on digital waveforms, dataflows, memory, and hierarchical viewers, may not be optimal for all applications. For example, in a waveform signal values are represented with respect to time, allowing many parameters to be verified in a digital system.

However, when large data sets are used or the correlation between non-linear values must be analyzed, engineers will often have too many screens of illegible alphanumeric data to review, losing precious time analyzing or investigating alternative methods to represent this data. For this reason, traditional tools might not be the most efficient debugging solution for data-intensive applications such as image processing, digital filtering, industrial control systems, telecommunication systems and certain embedded systems.

Riviera-PRO 2013.02 also includes debugging features such as virtual expressions in the Waveform and conditional expression-based breakpoints. Virtual signal expressions allow observing relations between different signals without having to do any additional coding for debug purposes only. Conditional breakpoints have a wide array of applications; for example, a breakpoint could now be set up on certain instance(s) of a SystemVerilog class.

Aldec has finalized all the major implementations in VHDL 2008 and continues to offer industry-leading support for this language standard and blossoming OS-VVM community. Simulation performance is another topic that has always been a critical priority for Aldec R&D labs. With Riviera-PRO 2013.02, users will see dramatic 1.5—2X improvement to gate-level netlist simulations and considerable speedup in regular Verilog/SystemVerilog and VHDL simulations.

Visit Aldec at www.aldec.com


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