Mixed signal design software simplifies platform management design
The integration of the PAC-Designer 6.1 and Diamond 1.3 design software tools will make more advanced digital design options available with Platform Manager products. An automated simulation environment, not previously available to Platform Manager designers, is a primary benefit of the design software integration.
Whether testing the functionality of critical analog I/O pin functions controlled by the Platform Manager’s internal CPLD, or checking the integration of enhanced digital control functions coded in Verilog or VHDL within the Platform Manager’s FPGA control section, PAC-Designer 6.1 software integrates seamlessly with Diamond 1.3 design tools to compile the entire design, create the necessary stimulus template file and then automatically generate initial timing waveforms within the Aldec Active-HDL simulator. This previously complex, manual design flow has been optimized and automated in PAC-Designer 6.1 software to generate all the necessary design files and deliver the initial timing flow diagram with just the click of a mouse.
Design Support PAC-Designer 6.1 software provides a GUI-based design methodology for analog engineers that uses intuitive dialog boxes to configure the Platform Manager’s analog sections; LogiBuilder design methodology to integrate power management functions into the on-chip CPLD; and LogiBuilder or Lattice Diamond Verilog/VHDL design methodology to integrate digital board management functions into the FPGA section of the Platform Manager device.
PAC-Designer 6.1 software includes four reference designs specifically targeted for the Platform Manager development kit, including Fault Logging and Monitoring, Enhanced Closed-loop Trim, Long Delay Timers and ADC Voltage Measurement. Eleven more reference designs compatible with Platform Manager devices are available on the Lattice website at www.latticesemi.com/products/powermanager/platformmanager, including, among others, PWM Fan Control, Connecting an I2C Slave to SPI Master Bridge and a BSCAN1 Multiple Scan Port Addressable Buffer. Thirty-one additional design examples are also available from directly within PAC-Designer 6.1 software that provide instructions and solutions for Power Manager II and ispClock devices.
Third Party Design Tool Support The integrated PAC-Designer 6.1 and Lattice Diamond 1.3 software includes the Synopsys Synplify Pro advanced FPGA synthesis for Windows. Aldec’s Active-HDL Lattice Edition II simulator is also included for Windows.
In addition to the tool support provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support Lattice devices.
Visit Lattice Semiconductor at www.latticesemi.com.
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