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Mixel MIPI C-PHY/D-PHY IP available on STM 40LP process

Mixel MIPI C-PHY/D-PHY IP available on STM 40LP process

Business news |
By Jean-Pierre Joosting



A high-frequency, low-power, low-cost, physical layer, the MIPI® C-PHY/D-PHY Combo IP from Mixel is now available on STMicroelectronics’ 40nm Low Power process technology (CMOS040LP).

The MIPI C-PHY IP supports the v1.2 specification, and the MIPI D-PHY IP supports the MIPI D-PHY v2.1 specification. The MIPI C-PHY IP mode supports a speed of 3.5 Gsps per trio, an equivalent data rate of 7.98 Gbps/trio, and in MIPI D-PHY mode, the IP supports speeds up to 2.5 Gbps per lane. With up to three trios in C-PHY and up to four lanes in D-PHY, the combo IP reaches an aggregate bandwidth of 23.94 Gbps and 10 Gbps in their respective modes.

There are multiple configurations of this combo IP available, including area optimized transmitters or receivers, supporting either the MIPI Camera Serial Interface 2 (CSI-2®) or MIPI Display Serial Interface 2 (DSI-2SM) as well as a universal version of the IP which supports all configurations. In addition, Mixel also offers its patented RX+ and proprietary TX+ versions of its MIPI receiver and transmitter IPs. These unique configurations allow full-speed, in-system testing without the area penalty of a universal configuration and are designed for safety sensitive applications such as automotive, medical, and other use cases where safety and reliability are critical.

Mixel’s IP achieved first-time silicon success on a test chip manufactured in ST’s 40nm low power process technology and other MIPI IP configurations are in development on another ST process technology.

“Mixel has been a valued Contributor member of MIPI Alliance and supporter of its specifications since 2006,” said Sanjiv Desai, MIPI Alliance chair. “By offering their silicon-proven MIPI IP in ST’s 40nm low power process technology, Mixel is actively playing a role in the growth of the MIPI ecosystem.”

This combo IP, silicon-proven at 4.5 Gsps per trio in C-PHY mode and 4.5 Gbps per lane in D-PHY mode, was first announced in September 2020.

“We worked very closely with the Mixel Engineering teams from pre-sales through silicon validation,” Pascal Mellot, Imaging System & Silicon Products Director at STMicroelectronics. “Achieving first-time silicon-success in this ST process is testament to Mixel’s engineering excellence and their long-proven methodology.”

“Achieving first-time silicon-success in ST’s process with this complex IP was only possible through the close collaboration between our teams, and an indication of ST’s process robustness and the excellence of Mixel engineering and methodology,” said Ashraf Takla, Founder and CEO of Mixel. “Expanding the availability of our MIPI IP in another ST process technology is helping expand IC development of our mutual customers in Europe and across the world.”

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