ML-based EDA tool automates digital chip design
The Cadence Cerebrus Intelligent Chip Explorer is designed to enable users to efficiently achieve demanding chip design goals. The combination of Cerebrus and the company’s RTL-to-signoff flow, says the company, offers advanced chip designers, CAD teams, and IP developers the ability to improve engineering productivity by up to 10x versus a manual approach while also realizing up to a 20% better power, performance, and area (PPA).
“Previously, design teams didn’t have an automated way to reuse historical design knowledge, leading to excess time spent on manual re-learning with each new project and lost margins,” says Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “The delivery of Cerebrus marks an EDA industry revolution with ML-driven digital chip design where engineering teams have a greater opportunity to provide higher impact in their organizations because they can offload manual processes. As the industry continues to move to advanced nodes and design size and complexity increase, Cerebrus lets designers achieve PPA goals much more efficiently.”
The new tool is cloud enabled and utilizes highly scalable compute resources from leading cloud providers to rapidly meet design requirements across a wide range of markets including consumer, hyperscale computing, 5G communications, automotive and mobile. Cerebrus is offered as providing the following benefits:
- Reinforcement ML: Quickly finds flow solutions human engineers might not naturally try or explore, improving PPA and productivity.
- ML model reuse: Allows design learnings to be automatically applied to future designs, reducing the time to better results.
- Improved productivity: Lets a single engineer optimize the complete RTL-to-GDS flow automatically for many blocks concurrently, allowing full design teams to be more productive.
- Massively distributed computing: Provides scalable on-premises or cloud-based design exploration for faster flow optimization.
- Easy-to-use interface: Powerful user cockpit allows interactive results analytics and run management to gain valuable insights into design metrics.
Cerebrus is part of the company’s broader digital full flow, and is designed to work seamlessly with the Genus Synthesis Solution, Innovus Implementation System, Tempus Timing Signoff Solution, Joules RTL Power Solution, Voltus IC Power Integrity Solution and Pegasus Verification System to provide users with a fast path to design closure and better predictability. The new tool and the broader flow support the company’s Intelligent System Design strategy, which is designed to enable pervasive intelligence for design excellence.
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