Modeling skew requirements for interfacing protocol signals in an SoC
All these are universally accepted and have some timing requirements which may be in form of input/output delay requirements or special timing requirements (like transition and skew requirements for different signals), which need to be taken care of at the STA end. In this article, we will be focusing on one of these – maximum and minimum skew between two signals.
Some of these protocols (like DDR) have requirement for a finite maximum skew (difference in delays) between the various signals of a bus. All data has to change within a very small timing window. On the contrary, minimum skew requirement is generally specified to prevent the race condition between two signals. This is usually one sided; e.g. signal ‘a’ should follow ‘b’ after some finite time. Until recently, these skew requirements were modeled in a roundabout manner and had to be updated regularly which adversely impacted the STA analysis time of each database as there were multiple iterations for IO constraints maturity.
Read the full article on page 23 of our July/August digital edition.
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