Modeling stress-induced variability at advanced IC process nodes
Feature articles
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By
eeNews Europe
A leading cause of systematic variability at advanced process nodes is the application of mechanical stress to transistors – even when the stress is applied intentionally to enhance performance in CMOS ICs. At 28nm and 20nm, in particular, design flows and EDA signoff tools must be able to analyze and mitigate stress-induced variability.
Read the full article on page 34 of our May digital edition.
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