Modular PCIe Gen 6 Controller IP supports diverse modes
US startup SignatureIP has launched modular controller IP for the next generation PCIe 6.0 protocol
The modular PCIe 6.0 IP natively integrates with SignatureIP’s iNoCulator tool for network on chip interconnect to provide a high-speed interface for chip design to seamlessly connect with peripherals.
The IP has been designed from the ground up so that there is no legacy code overhead ensuring a very small footprint as well as an outstanding operating frequency of 1 GHz for Gen 6 data rate. The power consumption can be further reduced by clock gating and power gating in the power management unit.
- NoC startup offers free trial of configuration tool
- First IP interoperability with Intel PCIe6.0 test chip
- Full customisation tool for Semidynamics RISC-V cores
The PCIe Controller is provided as synthesisable RTL along with sample test benches and tests for easy implementation along with scripts for simulation, syntheses and timing. As with all SignatureIP products, full documentation is provided for integration into a customer’s design.
“As we have designed this from scratch, we have made it modular so that features can be added or deleted to exactly meet the customer’s requirements,” said Kishore Mishra, chief technology officer at SignatureIP.
“The configuration registers are implemented as a part of the IP and ihas a layered architecture with PHY layer, Data link layer and Transaction layers. Trace and debug features are built in for rapid implementation so that the customer has a fast time to market.”
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