Momentum builds for 3-D chips
The progress remains slow and the technology still appears to be in the ”power point’’ stage.
Still, the IC industry is moving full speed ahead with a monumental and costly push to develop TSV-based 3-D chips. A plethora of companies, including IBM, Intel, Samsung, Toshiba, TSMC and others, are exploring the possibility of stacking current devices in a
3-D configuration.
At the 2011 GSA Memory Conference on Thursday (March 31), four industry organizations-IMEC, ITRI, Sematech and SEMI-separately made presentations about the latest progress within their respective entities for 3-D chips based on TSV.
A 3-D working group within SEMI met for the first time this week to sketch out the initial wafer and tool standards for TSV technology. SEMI has three task groups within its 3-D group. A fourth group is being formed, which may be led by Applied Materials Inc.
In a separate program within Sematech, the chip-making consortium is expanding its own 3-D program. One surprising chip maker, Analog Devices Inc., is joining Sematech’s ”3-D Design Enablement Center.’’ Altera, LSI, On Semiconductor and Qualcomm are also part of the center.
A plethora of others are also scrambling to develop TSV-based technology-and for good reason: There are fears that IC scaling is becoming too costly for most chip makers-or will end in the distant future.
So instead of scaling, there is another concept on the table: stack and connect devices in a 3-D configuration using TSVs. For years, chip makers have been talking about 3-D chips based on TSVs. But except for select products-such as CMOS image sensors-the technology has not moved into the mainstream, due to costs, lack of standards and other factors.
In theory, 3-D chips could evolve in two steps. The first step is a 2.5-D scheme using silicon interposers. Then, eventually, the industry could move to TSV-if it can solve the multitude of problems with the technology.
Right now, there are several new and mainstream 3-D chip projects in the works. For example, Semtech is working with IBM and its 3-D TSV technology to develop a combination analog-to-digital converter and DSP platform. These two different technologies are connected through a single wiring layer on an interposer, which supports a bandwidth of greater than 1.3-Tbps.
Last year, Xilinx announced the industry’s first stacked silicon interconnect technology for delivering breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density. By embracing 3-D packaging technologies and TSV for its 28-nm 7 series FPGAs, Xilinx’s can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. Initial devices will be available in the 2nd half of 2011.
In a separate effort, Hynix, Samsung and others have identified a new device vehicle that could propel TSV-based 3-D chips into the mainstream: a wide I/O DRAM for cell phones, tablets and related products.
Wide I/O, a memory interface standard in review at JEDEC, defines a 512-bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8- gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions.
Today, mobile DRAM is based on a technology called low-power double data rate 2 (LPDDR2). Beyond LPDDR2, Samsung and others are pushing wide I/O DRAM for mobile applications. Wide I/O will evolve in two phases. The first wide I/O DRAMs are four-partitioned devices, which will be stitched together via micobumps. They are expected to appear in 2013.
In the future, vendors hope to stack multiple wide I/O DRAMs using TSVs. Some say those devices will appear in 2014 or 2015. Some believe the technology will appear later than sooner. Due to the complexity and costs, TSV-based wide I/O DRAM will not arrive until ”the second half of the decade,’’ said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus Inc.
Holt also does not believe the industry will directly migrate from LPDDR2 mobile DRAM to wide I/O DRAM. LPDDR2 mobile DRAMs began shipping last year, but wide I/O DRAM will not appear for some time.
As a result, there is a time gap between the two technologies. Not surprisingly, Rambus is pushing mobile XDR, one of the many next-generation mobile DRAM technologies in the market.
During a keynote address at the GSA event, Holt also said that there could one day be a convergence between today mobile and PC memory. In other words, some of the low power technologies in mobile DRAM could migrate to PC DRAM, creating what Holt called a ”unified memory system.’’
Others have a different idea. At the GSA event, Jim Elliott, vice president of marketing and product planning at Samsung Semiconductor Inc., said there could be a convergence in DRAM technology, but he noted that convergence involves a wide I/O product based on TSV.
But one of the problems with TSV is the lack of standards. In December, SEMI moved to reverse the problem by forming the Three-Dimensional Stacked Integrated Circuits (3DS-IC) Standards Committee.
To gather industry input and identify potential standardization topics, SEMI is working with Sematech to identify areas of concern for 3D TSV integration. Sematech represents several companies, including Globalfoundries, HP, IBM, Intel, Samsung, and UMC. Other companies supporting the formation of the 3DS-IC Standards Committee include Amkor, ASE, IMEC, ITRI, Olympus, Qualcomm, Semilab, Tokyo Electron and Xilinx.
The 3DS-IC Standards Committee will initially consist of three Task Forces:
•Bonded Wafer Pair (BWP) Task Force: This group will create a standard for BWP, using SEMI M1 (Specifications for Polished Single Crystal Silicon Wafers) as a starting point. Sematech is the task force leader.
•Inspection and Metrology Task Force: With no existing standards in place, the group will seek to identify and create new standards that address deficiencies for metrology and inspection created by 3DS-IC. Semilab is the task force leader.
•Thin Wafer Carrier Task Force: Currently no standards exist so this group will identify and create new standards for thinned wafer carriers to address deficiencies created by 3DS-IC. Qualcomm is the task force leader.
Another task force is being formed, which will focus on a ”single wafer used in a stack process,’’ said James Amano, director of international standards at San Jose-based SEMI. That task force will be possibly led by Applied Materials Inc., he said.
The 3DS-IC Standards Committee met earlier this week to hammer out the first standards for ‘’wafer parameters’’ and other technologies, he said. A draft specification is due early next year, he said.
In another step toward driving the maturity of 3-D IC integration, Sematech’s 3-D Interconnect program last year announced the completion of its 300-mm 3-D IC pilot line, operating at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex in Albany, New York.
Sematech’s 3-D program includes Globalfoundries, HP, IBM, Intel, Samsung, TSMC, UMC and CNSE. Sematech is devising a ”reference flow’’ to enable the production of a wide I/O device, with a TSV that is 5 microns wide and 500 microns deep, said Sitaram Arkalgud, director of Sematech’s 3-D Interconnect Program.
In another piece of the puzzle, Sematech, the Semiconductor Industry Association (SIA), and Semiconductor Research Corp. (SRC) last year established a new 3-D Design Enablement program to drive industry standardization efforts and technical specifications for heterogeneous 3-D integration for a range of applications.
One of the eventual goals is to devise ”test reticles’’ based on 3-D for a range of applications, Arkalgud said. So far, the center’s members include ADI, Altera, LSI, On Semi and Qualcomm.
Sematech has also recently demonstrated a novel die-to-wafer interconnect process using a die-tacking and collective-bonding approach on a 300-mm wafer platform for 3D-IC applications. Composite wafers containing a 50-micron thin TSV wafer attached to a supporting handle wafer were populated with dice using a short, low-temperature tacking process. This process enables a faster method of die-to-wafer integration needed for the advancement of heterogeneous 3D-IC.
Wafer-to-wafer bonding is a key enabling process step for 3-D interconnection of wafers through stacking. The International Technology Roadmap for Semiconductors (ITRS) roadmap for high density, intermediate level, TSVs specifies via diameters of 0.8- to 4.0-micron in 2012 and beyond.
Sematech’s rival, IMEC, also has a major 3-D chip program. Earlier this month, Cascade Microtech Inc. and IMEC announced they entered into a collaborative research partnership for testing and characterization of 3D IC test structures. IMEC will work closely with Cascade Microtech to develop test methods and methodologies for emerging 3-D TSV structures, and to lead the way in development of global standards for 3D IC development and production test.
The complexities of test inherent in new 3D-TSV IC designs will be a key focus of the research project that will take place at IMEC’s research facilities in Belgium, where silicon wafers with test probe structures of 40 micron pitch and smaller will be manufactured and tested. In the process of ongoing research, IMEC will install the first turnkey 3D test solution comprising of a 3D-TSV probe station and a new 3D-TSV probe card from Cascade Microtech. The probe station and probe cards will be used to characterize the TSV in the chip stacks as part of ongoing efforts to optimize 3D stacked IC performance and reliability.
There are other 3-D efforts in the market. France’s CEA-Leti research center in Grenoble has begun to ramp up production on its 300-mm wafer fabrication facility dedicated to 3D-integration applications. CEA-Leti is known to be a close partner of STMicroelectronics and plans to work with Shinko Electric Industries Co. Ltd., a developer of silicon interposer substrates.
Singapore’s Institute of Microelectronics (IME), a research group, recently launched a consortium in 3-D packaging. Taiwan’s ITRI also has a 3-D consortium, which includes 22 members. Last year, Elpida Memory, Powertech Technology and United Microelectronics (UMC) formed an alliance to speed up the development of 3-D chips at the 28-nm node as well as other processes.
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