Moore’s Law extended again?
Using a method IBM pioneered called template-assisted selective epitaxy (TASE), IBM says it has proven the concept by fabricating a variety of nanoscale Hall structures and multi-gate FETs.
The cooperative efforts of the two labs appear to have achieved what semiconductor manufacturers around the world have been trying to do for many years, including Intel. In its paper published in Applied Physics Letters, IBM cites several partially successful techniques used by others to overcome the lattice mismatch between silicon and III-V materials (including indium, gallium, arsenide and their compounds) as well as earlier efforts to make its own template-assisted selective epitaxy (TASE) work.
However, it now claims to be the first to fabricate the complex and versatile structures needed to manufacture hybrid silicon/III-V transistors, including constrictions along a nanostructure, nanowire cross junctions, and 3D stacked nanowires — "an important step toward making future computer chips that will allow integrated circuits to continue shrinking in size and cost even as they increase in performance," according to the AIP and Senior Researcher Heinz Schmid at IBM Research GmbH at Zurich Research Laboratory in Switzerland, the lead author on the paper.
According to AIP, Schmid and associates accomplishment may also lead to active photonics on silicon substrates, since III-V materials are routinely used to make on-chip lasers and other photonic structures.
In more detail, the III-V materials use template-assisted selective epitaxy (TASE) with metal organic chemical vapor deposition to grow defect-free indium, gallium arsenide (InGaAs) structures — mainly wires — along an oxide template previously deposited and filled-in using epitaxy. As a result, Schmid reports pure crystalline III-V structures atop silicon with virtually zero defects using methods compatible with standard CMOS processing.
Schmid asserted that template-assisted selective epitaxy laid a solid foundation to the integration of III-V materials with silicon, but cautioned about being overly optimistic about the new TASE method, noting that more development and optimization will be needed to fabricate transistors and other structures as complex as today’s CMOS transistors, asserting that TASE presented "a very attractive prospect for the continued development of semiconductor circuits [using] large silicon carrier wafers on which multiple semiconductors with high mobility can be placed and co-integrated in an economically viable fashion," in the introduction to the paper.
To test the technique with real devices, Schmid and his co-authors, described the construction of "multiple gate field effect transistors (MuG-FETs) and nano-scale Hall bar structures," which they characterized using transmission electron microscope (TEM) analysis "to achieve dislocation-free material, suitable for hetero-integration of III-V materials on Si for III-V CMOS as well as optoelectronic applications."
Starting with Soitec SOI substrates e-beam lithography and reactive ion etching achieved devices of from 25-to-50 nanometers thick which were patterned atop a 30 nanometer thick layer of silicon dioxide laid down ahead of time with atomic layer deposition (ALD) and annealed at 850 degrees Celsius (1472 degrees Fahrenheit).
The paper contains many scanning electron microscope (SEM) images detailing all the steps taken to fabricate the hybrid FET and Hall structures resulting in electron mobilities of up to 5400 cm2/Vs (compared to silicon mobility of 1400 cm2/Vs).
See all the details in the American Institute of Physics (AIP) Applied Physics Letters paper for free.
— R. Colin Johnson is Advanced Technology Editor at EE Times