Moore’s law has no end in sight
The handwriting has been on the wall since the 1980s, according to former Bell Labs scientist, now co-founder and chief scientist at POET, Geoff Taylor.
According to Taylor, GaAs, as opposed to silicon, will boost electrical transistor performance while integrating optical circuitry capabilities. These qualities enable both higher performance and novel IC architectures, thereby extending Moore’s Law indefinitely.
"Silicon digital logic hits the wall at 4 GHz, but we can produce small gallium arsenide [GaAs] analog circuits switching at 100 GHz today and 400 GHz in the not too distant future," he tells EE Times. "Plus POET fabricates optical emitters and detectors for on-chip optical interconnects."
Combining standard logic with optical components on the same chip also changes the design methodology, prompting a collaboration with Synopsys, Inc., of Hillsboro, Ore., to help design hybrid electro-optical devices. For instance, an optical loop achieves an ultra-low jitter oscillator with higher bandwidth than silicon, according to POET. By going to multi-wave lengths, POET also aims to build ultra-precise analog-to-digital converters by encoding voltages as wavelengths, resulting in higher resolution and bit rates with reduced power and fewer components.
POET’s indium gallium arsenide ring oscillator is more accurate than silicon and can reach higher frequencies. (Source: POET)
Other advantages of III-V over silicon is its lower operating voltage — as low as 0.3 volts with electron mobilities as high as 12,000 cm2/ (V·s) achieved by strained quantum wells — lowering the power required to operate III-V chips by 10 times or more, according to POET.
Of course, GaAs wafers are more expensive than Si, but the next generation of Si is already using silicon-on-insulator with fully depleted (SOI-FD) transistors, a technology that costs almost as much as GaAs, according to Taylor.
Most III-V elements, including indium (In), gallium (Ga), arsenide (As), and phosphorous (P) have much higher electron mobility than silicon, but have special fabrication problems that have prevented them from already taking over silicon — namely, the lack of enhancement devices for digital circuits and of the p-channel transistor for complementary design. However, POET has found a way to grow successive layers of InGaAs on GaAs wafers, each with a little more indium, until they achieve a substrate on which both n-type and p-type transistors can be fabricated.
The p-types could ultimately achieve about a 1900 cm2/(V·s) hole mobility in the strained InGaAs quantum well, which is not as high a figure as the n-types, which achieve 8500 cm2/ (V·s). Both are higher than silicon, at 1200 cm2/ (V·s). POET has high hopes that it can eventually boost the n-types to greater than 12,000 in order to realize extremely high digital logic rates with complementary HFETs.
Taylor had moved on to the University of Connecticut for several years before the Bell Labs patents expired on III-V chips. It was there that he resurrected the Bell Labs work, but transformed it from a single n-channel-only electrical/optical (EO) technology into a dual-channel electrical/optical technology aimed at extending Moore’s Law indefinitely well into the future for complementary electrical/optical circuits. He renamed the technology Planar Opto Electronic Technology (POET). The University of Connecticut is now assigned the patents, with POET its exclusive licensee.
"Our planar electronic technology – called PET – is a major advance over previous GaAs technologies based on NMOS-like circuit structures, because we have integratable in-plane optical and electrical devices that are complementary – so you can do CMOS," Daniel DeSimone, chief technical officer tells EE Times.
The channels of POET’s transistors are InGaAs, which theoretically could reach 40,000 cm2/ (V·s) if the gallium was reduced to zero (pure bulk InAs). That however is not achievable, according to POET, although it is getting as close as it can. Thus far channels of 53% indium have been achieved and the company believes that 80% indium is ultimately possible.
POET’s use of GaAs substrates allows it to include optical devices alongside electrical devices, allowing transistors and optical interconnects to co-exist on the same chip. (Source: POET)
"We achieved these results by changing the lattice constant in a unique metamorphic way that fools nature," Taylor tells EE Times. "First we start with GaAs substrate, then we layer on top of that one micron strained layers of InGaAs over and over until we reach a layer that has natural quantum wells corresponding to the lattice constant of InP. It’s all a question of the compositional control enabled by MBE [Molecular-beam epitaxy]."
POET has a deal with a third-party foundry to demonstrate a 100 nanometer process later this year and a 40 nanometer process by 2015. Those figures sound like they are behind silicon, which is already down to 20 nanometers and, at Intel, down to 14 nanometers. But POET argues that the comparison is not fair. Instead its 40 nanometer process should be compared to 14 and 10 nanometer in silicon.
"Our 40 nanometer GaAs compares to silicon 3 nodes ahead in speed and 4 nodes in power, with comparable integration density," DeSimone tells EE Times. "Thus 40 nanometer GaAs compares to 14 nanometer in speed and 10 nanometer in power."
— R. Colin Johnson, Advanced Technology Editor, EE Times
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Moore’s lag shifts paradigm of semi industry
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