Moortec recasts in-chip thermal sensor for TSMC N5 process
The result is a considerable space saving and the opportunity, deploy many more probes and do fine-grained thermal feedback, which is increasingly being used in application software as part of load-balancing and functionality.
Moortec has been supplying process, voltage and thermal (PVT) sensor IP for semiconductor manufacturing processes since the company’s formation in 2005. Early use of this technology was to perform the simple shut down to protect a system or chip from overheating. This has moved on to providing thermal information as an indicator of processing activity for use in dynamic voltage and [clock] frequency scaling (DVFS).
The company has now come up with a distributed thermal sensor (DTS) that allows up to 16 sensor probes to be distributed across an area of die and communicate back with a hub and on to a PVT controller. As with previous iterations of the thermal sensor IP multiple such sensor nodes can be included on a die.
But in the DTS version it can run off core voltage supply rather than the I/O supply Vdd. Each sample point is 2 percent the size of the previous generation of thermal sensor and even with 16 sample points and the control hub there is a 7x area saving, Moortec said.
The DTS generation of thermal IP is targeting TSMC’s 6nm, 5nm and lower manufacturing process nodes. The company said it may opt to also go back up to the popular 7nm node. The accuracy of the DTS probe is similar to the previous generation at +/-5degreeC uncalibrated and +/-1degreeC calibrated.
But the ability to sprinkle multiple probe points across the die with little area cost can make for a more fine-grained and accurate understanding of thermal hot spots and a better response to them.
“We’ve seen a clear need for tighter thermal control of semiconductor devices,” said Stephen Crosher, CEO of Moortec, in a statement. “Multicore architectures applied to AI, automotive, consumer and many other applications, benefiting from highly distributed sensing schemes to minimize system-level power consumption, optimize data throughput, and improve product lifetimes.”
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