More flexibility for power management chip designers, says ARM
DynamIQ allows groups of cores within a CPU cluster such as the latest ARM A-75 and A-55 cores to be designed with independent voltage and frequency domains with independent power rails to groups of cores. This provides more choice for designers using a big.LITTLE topology with a large core such as the A-75 and several smaller A-55 cores.
The new architecture can support up to 8 A-55 cores, up from four for the previous generation A-53. This provides finer grained domains for additional power saving opportunities so that the large cores can be shut down in thermally constrained applications.
DynamIQ does not require a specific number of power rails to function says ARM. The designs are fully configurable to scale from the same number of power rails as conventional Cortex-A CPU clusters to higher counts for finer control.
ARM provides guidance to customers around this topic it says but as they don’t control the end system-on-chip design and they don’t specify the number of power rails or the number of cores per power rail, these are decisions that are taken by the chip designers. This means is the semiconductor partners that then drive the discussions with PMIC power management chip makers on specific requirements to support their SoCs.
As an example of the complexity for PMIC developers, Qualcomm’s Snapdragon 845 that is scheduled for production in Q1 of 2018 on a 10nm process is using four A75 DynamIQ cores and four of the previous generation A53 cores.
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