MRAM switching current measurement technique for memory test

MRAM switching current measurement technique for memory test

Technology News |
By eeNews Europe

This makes it possible to observe the microampere changes in the currents that flow through STT-MRAM memory cells, and represents a signficant move forward for STT-MRAM failure analysis and eventually practical application of STT-MRAM technology via the development of a test system using the newly developed technology. This testing technology is available for not only STT-MRAM but also other resistance change type memory such as ReRAM and PCRAM.


STT-MRAM memory cells consist of magnetic tunnel junctions (MTJs) and transistors. which Memory cells are arranged in stacks to form memory arrays. An MTJ is a nonvolatile memory element which utilizes magnetoresistances to record data. In addition to not requiring standby power, STT-MRAM combines all the characteristics of high-speed operation, low-voltage operation, and high rewrite tolerance which are said to be difficult to achieve with other nonvolatile memory technologies.

For this emerging technology to be developed for volume production, highly efficient and accurate performance evaluation using memory test systems will be essential. However, current switching in STT-MRAM is a probabilistic phenomenon which exploits the quantum-mechanical properties of electrons, and is subject to thermally induced fluctuations. Additionally, these currents are very weak, at 100 microamperes or less, and flow only for nanoseconds at a time. This means that even though measurement instruments can be used to measure switching on a single magnetic tunnel junction, or on one memory cell, it has been difficult to measure it on memory arrays containing multiple memory cells.

To address this, the team, led by  Prof Tetsuo Endoh in the Graduate School of Engineering at Tohoku, developed a high-precision, high-speed current measurement module for an Advantest memory test system which measured the minute changes in resistance and the variation distribution of current transition times during STT-MRAM switching operations, in units of nanoseconds.

In the experiment, an STT-MRAM test chip which composed of memory cells containing one MTJ and one transistor was prototyped on a 300mm silicon wafer—the standard size used in the industry—and the whole surface of the wafer was measured. This success marks the development of a technology for analyzing defects in STT-MRAM with high efficiency and high precision. It is hoped that it will lead towards improving yield rates and putting STT-MRAM into practical use.

Tohoku University CIES will continue research and development activities aiming to commercialize a new STT-MRAM memory test system equipped with an external magnetic field application mechanism.

Related stories:



If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles