The XLP II processor family is designed to deliver over 100 Gbit/s of network processing performance per device, and over 800Gbit/s in a clustered, fully-coherent system. The XLP II multi-core processors integrate up to 80 high-performance NXCPUs per chip, featuring an enhanced quad-issue, quad-threaded, superscalar out-of-order processor architecture capable of operating at up to 2.5 GHz to provide unmatched control and data plane processing and low-power profile. These processor cores include advancements that considerably improve pre-fetch performance, branch mis-predict penalties and cache access latencies. The XLP II multi-core processor family also significantly expands the tri-level cache architecture to over 32MB of fully coherent on-chip cache which represents over 260MB of on-chip cache in the maximum clustered configuration of 8 fully-coherent XLP II processors.
To further extend the performance and capabilities of the XLP II processors, customers will be able to design systems using eight sockets of XLP II processors to achieve an unprecedented scalability of up to 640 NXCPUs. A second-generation high-speed Inter-chip Coherency Interface (ICI) enables full processor and memory coherency across all 640 NXCPUs, making it seamless for software applications to run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes.
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