Multi-core control-plane processor for LTE communications infrastructure

Multi-core control-plane processor for LTE communications infrastructure

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By eeNews Europe

Control-plane processing requirements in 3G/4G LTE mobile infrastructure are increasing exponentially due to the significant growth in signaling traffic from smartphones and tablets. Always-on mobile broadband applications that run on these data-centric devices make frequent connections to the network to check for updates to emails and social networking sites, as well as to perform other background processes. The accumulation of these frequent bursts of signaling traffic is placing an unprecedented burden on control-plane processing that requires new levels of processing horsepower while maximizing energy efficiency in next-generation mobile infrastructure equipment.

In addition, the industry migration to IPv6 networking, driven by the exhaustion of IPv4 addresses, is creating significantly higher control-plane processing requirements. Because IPv6 generates over 28 orders of magnitude more Internet addresses than its predecessor, this dramatically increases the burden on control-plane processing to manage and update the complex IPv6 databases.

The innovative XLP316 processor is ideally suited to address new levels of control-plane performance requirements by combining a powerful multi-core processor architecture with a high-performance floating point unit and a low latency tri-level cache architecture. When compared to competing quad-core processors with dual-issue and single-threading per core, in-order execution and missing L3 cache, the XLP316 delivers up to 400 percent higher control-plane processing performance, which enables original equipment manufacturers (OEMs) to develop advanced, scalable systems for next-generation LTE and IPv6 networks.

“Having the industry’s only quad-issue, quad-threaded communications processor family with on-chip L3 cache gives us an enormous competitive advantage to address the most demanding control-plane processing requirements,” said Chris O’Reilly, vice president of marketing at NetLogic Microsystems. “The combination of the superior and highly optimized architecture along with the advanced 40-nm process gives us further advantage in delivering the lowest power profile to meet our customers’ stringent requirements.”

The XLP316 multi-core processor integrates 16 NXCPUs™ which are fully cache and memory coherent for software applications to seamlessly run in Symmetric Multi Processing (SMP) or Asymmetric Multi Processing (AMP) modes. The 16 NXCPUs are efficiently interconnected via NetLogic Microsystems’ high-speed, low-latency Enhanced Fast Messaging Network™ to support billions of in-flight messages and packet descriptors between all on-chip elements.

The XLP316 multi-core processor offers a tri-level cache architecture with 4 Mbytes of L3 cache and over 6 Mbytes of fully coherent on-chip cache which delivers 40 Terabits per second (Tbps) of extremely high-speed on-chip memory bandwidth. The XLP316 processor also incorporates one channel of 72-bit DDR3 interconnect that yields over 100 Gbps of off-chip memory bandwidth.

Further the multi-core processor family is supported by a comprehensive software development kit (SDK) that contains reference and production-ready software components, which enables customers to accelerate time-to-market.

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