The parts are multi-channel jitter attenuating clocks for 4.5G and Ethernet-based Common Public Radio Interface (eCPRI) wireless applications, and employ Silicon Labs’ DSPLL technology to deliver a timing solution that combines 4G/LTE and Ethernet clocking in a single IC. With Ethernet becoming prevalent in wireless backhaul, there is a need for versatile clock sources that offer the lowest possible phase noise and spurious signal content; Silabs says it has delivered this in these devices, with a high level of integration. Stability is provided using the company’s two-stage, “nested” DSPLL technique; this provides both jitter cleaning and the required clock generation in one functional block.
Following Silabs established business model, these parts are programmable to specified frequency outputs using embedded non-volatile memory (as opposed to metal-mask programmed); they are factory programmed by an automated, on-line-ordering process (“ClockBuilder Pro”), with rapid delivery promised.
The integrated clocks eliminate the need for multiple clock devices and voltage-controlled crystal oscillators (VCXOs) in applications including small cells, distributed antenna systems (DAS), baseband units (BBU) and fronthaul/backhaul equipment. Application scenarios for the two parts are summarised in this diagram;
Silabs notes that, as carriers transition to Ethernet-based eCPRI fronthaul networks to increase the capacity of fronthaul connections between base band units and remote radio heads, they are also deploying heterogeneous network (HetNet) equipment at the edge of the network where cost, power and size constraints present unique challenges for hardware designers. By combining 4G/LTE and Ethernet clocking in a single IC, the Si538x family simplifies HetNet clock generation, providing a solution that is claimed to be 55% lower power and 70% smaller than alternatives. The company continues, “Silicon Labs’ DSPLL-based Si538x clocks are the industry’s first timing ICs that combine low-phase-noise 4G/LTE clocking and low-jitter Ethernet clocking in the same device.”
The Si538x clocks are optimized to provide reference timing for HetNet equipment. Small cells and DAS equipment are “all-in-one” base stations that need reference timing for 4G/LTE transceivers, baseband processing and Ethernet/Wi-Fi connectivity. The Si5386 clock’s low-phase-noise DSPLL replaces a discrete clock IC, VCXO and loop filter components in a compact, single-chip design. In addition, the Si5386 clock integrates five MultiSynth fractional clock synthesizers to provide simplified Ethernet and baseband reference timing. This streamlined, single-PLL design provides superior reliability to alternate solutions that rely on multiple PLLs and discrete oscillators.
Baseband units have complex timing requirements requiring multiple independent clock domains for CPRI or links to remote radio heads, Ethernet-based eCPRI for fronthaul networks and general-purpose clocks for local baseband processing. The Si5381/82 clocks combine a high-speed, low-phase-noise DSPLL supporting wireless frequencies up to 3 GHz with flexible any-rate DSPLLs optimized for Ethernet and general-purpose timing. Like the Si5386 clock, the Si5381/82 devices require no external VCXOs or crystals. All PLL components are integrated on-chip in a 9 x 9 mm 64-LGA package. The Si538x clocks support a hitless switching capability that enables system designers to switch between different clock inputs and minimize phase transients, ensuring downstream PLLs remain in lock.
Samples of the Si5381/82/86 wireless clocks are available, and production quantities are planned to be available in December 2017. Samples ship in two weeks, and production quantities are available in four weeks. Pricing starts from $6.77 (10,000) for the Si5386 clock. the Si5381E-E-EVB, Si5382E-E-EVB and Si5386E-E-EVB development kits are priced at $299 each
Silicon Labs; www.silabs.com/wireless-jitter-attenuators