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Multichip output synchronisation by 5-output ultralow-jitter clock IC

Multichip output synchronisation by 5-output ultralow-jitter clock IC

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By eeNews Europe



Maintaining low jitter on the data converter clock is fundamental to achieving outstanding SNR levels when digitising or synthesising high analogue frequencies. For instance, modern electronic systems demand direct digitisation of RF and high IF signals using an ADC. With 18fsec RMS jitter (over the 12 kHz to 20 MHz bandwidth), the LTC6950 guarantees the best performance out of such a system.

The LTC6950 incorporates Linear Technology’s EZSync output synchronisation, a simple, effective method to edge-synchronise multiple outputs from either one chip or multiple chips. EZSync synchronisation aligns the rising edges by simply asserting a common CMOS input with loose timing requirements. It can also be used to produce repeatable and deterministic phase relationships between the clock divider outputs of devices that have this feature enabled.

The phase-locked loop (PLL) inside the LTC6950 has a normalised in-band phase noise floor, or figure-of-merit, of -226 dBc/Hz and exceptionally low -274 dBc/Hz normalised 1/f phase noise which stays intact going through the clock distribution section. These specifications ensure designers take full advantage of the good phase noise performance of the external oscillator that is being locked by the LTC6950 and deliver the best jitter performance in this class of parts.

To simplify the design process of the LTC6950, Linear Technology offers the ClockWizard free simulation and design tool. The ClockWizard GUI helps find loop filter component values with a click of a button, and accurately predicts the individual output’s phase noise and jitter, helping the designer make the correct choices during the design and debug phases. The ClockWizard simulation and design tool can be downloaded at www.linear.com/ClockWizard

The LTC6950 is specified over the full operating junction temperature range from -40°C to 105°C. It is available in a 5 x 9 mm, 48-lead plastic QFN package for $9.95 (1,000).

Linear Technology; www.linear.com/product/LTC6950

next page; feature list


Summary of Features: LTC6950

Low Phase Noise & Jitter

Additive Jitter: 18 fsecRMS (12 kHz to 20 MHz)

Additive Jitter: 85 fsecRMS (10 Hz to Nyquist)

EZSync Multichip Clock Edge Synchronisation

Full PLL Core with Lock Indicator

-226 dBc/Hz Normalised In-Band Phase Noise Floor

-274 dBc/Hz Normalised 1/f Phase Noise

1.4 GHz Maximum VCO Input Frequency

Four Independent, Low Noise 1.4 GHz LVPECL Outputs

One LVDS/CMOS Configurable Output

Five Independently Programmable Dividers Covering All Integers from 1 to 63

Five Independently Programmable VCO Clock Cycle Delays Covering All Integers from 0 to 63

-40°C to 105°C Operating Junction Temperature Range

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