Mythic upgrades RISC-V core for next AI processor
Analog compute-in-memory chip developer Mythic is to license another RISC-V core from Codasip in Germany for a new generation of AI processor.
The L30 RISC-V core (originally the Bk3) core will be used in Mythic’s Analog Matrix Processor (AMP). The AMP processor is designed with an array of tiles, each containing a large Analog Compute Engine (ACE) to store neural network weights and perform matrix multiplications; local SRAM memory for data being passed between the neural network nodes; a single-instruction multiple-data (SIMD) unit for processing operations not handled by the ACE; and a Codasip processor for controlling the sequencing and operation of the tile.
Mythic customized the processor IP to meet the unique computing requirements of the AMP using Codasip Studio.
This follows a deal in 2018 to use the Codasip Bk5 RISC-V core with the M1108 processor with 108 cores launched in November 2020. The M1076 processor with 76 tiles was launched in June 2021 to fit into an M.2 form factor (above)
- RISC-V boom from edge AI says Facebook’s chief AI scientist
- Mythic AI adopts RISC-V core from Codasip
- Industry-first AI analog matrix processor launched
- Three RISC‑V cores add multi-core and SIMD for edge AI
“Codasip’s RISC-V cores and customization toolset helped us accelerate the design of our new M1076 AMP while giving us the flexibility we needed to offer an unparalleled combination of performance and power efficiency,” said Ty Garibay, Vice President of Engineering at Mythic. “We look forward to continuing our engagement with Codasip on the next generation of our groundbreaking processors for cutting-edge AI applications.”
“We have been thrilled to see the launch of Mythic’s revolutionary Analog Matrix Processor,” said Dr. Karel Masařík, CEO and Founder of Codasip, “We are very excited to have been chosen for the company’s next artificial intelligence processor design.”
The Codasip L30 processor is based on the RISC-V open instruction set architecture (ISA) and optimized for low power and area efficiency. It has a single 3-stage processor pipeline architecture, optional caches, optional Floating Point Unit, Multiplication and Division, JTAG and RISC-V debug, and industry standard bus interfaces (AMBA). It also includes support for privilege-mode and memory protection via standard RISC-V PMP.
Other related articles
- Codasip opens RISC-V design centre in France
- Micron, Lam help raise Mythic’s Series B to $70m
- Custom graphics extensions boost RISC-V
Other articles on eeNews Europe
- Post-quantum chip has built-in hardware Trojan
- Two UK universities launch 6G centre
- Don’t dabble says onsemi chief in re-brand
- Samsung moves to 5nm EUV for wearable chips
- John Deere in $250m autonomous tractor tech deal
- Infineon teams for smart glasses and head-up displays