NAND, DRAM 3D-transition roadmaps
In mid-2014, the most advanced process technology used to make NAND flash devices was based on 20nm and smaller feature sizes, and just under 30nm for DRAMs. The process technology roadmaps shown in Figure 1 suggest that by 2017, the minimum feature size for 2D (planar) NAND flash will migrate to 10-12nm and to 20nm or less for DRAM.
However, IC Insights admits that such developments are hard to pin down because the definitions manufacturing process nodes are imprecise and may be influenced by marketing "numbers games" as companies try to get an advantage over their competition.
Volume production NAND flash and DRAM roadmaps. Source: IC Insights.
In manufacturing NAND flash memory, high-volume production of 15nm/16nm NAND chips has been ramping up in 2014. The first company to mass-produce 3D NAND chips was Samsung. In May 2014, the company announced that it had started volume production of its V-NAND flash chips using 32 memory cell layers. The company had previously shipped a limited number of solid-state drives (SSDs) based on its first generation 24-layer V-NAND technology to some of its data center customers in 2013.
The timing of a full-scale transition from 2D to 3D NAND memory depends on the point at which 3D becomes a cost-effective option to 2D, and that situation is still a ways off. Even when the cost crossover point is reached, 2D and 3D NAND will likely coexist for several years.
Leading DRAM makers are currently manufacturing at volume production using 20nm-class feature sizes (between 20-29nm).
Like NAND flash, DRAM technology is also migrating toward integrating circuitry in the vertical direction. One example of a 3D DRAM solution is the Hybrid Memory Cube (HMC), developed by the consortium of the same name. The Hybrid Memory Cube Consortium was founded by Micron and Samsung and includes other developer members Altera, ARM, IBM, Open-Silicon, SK Hynix, and Xilinx.
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