Nanium to offer Fan-In wafer-level packaging in volume on 300mm wafers
Earlier this year, the company licensed Flip Chip International’s (FCI) Spheron Plated Cu Redistribution technology to provide solutions for 300mm wafer-level chip scale packaging (WLCSP) using fan-in WLP processes. After completing line setup and qualification for that technology, the company has added the capability to manufacture fan-in WLP products.
“The conventional fan-in variant of WLP on the silicon wafer, where all IOs are located on the die, offers a cost-effective solution for the required package size, IO count and performance of many IC products,” said Armando Tavares, president of Nanium’s executive board. “By leveraging our proven WLP processes and know-how, NANIUM is now extending its service offer to cover the full range of wafer-level packaging requests of our customers, fan-in and fan-out.”
Wafer-level chip scale packaging (fan-in WLCSP) enables low-cost manufacturing of small die sizes, with low I/O density, and high performance. The technology includes the re-passivation, redistribution (RDL), under-bump metallization (UBM), bumping, test, laser marking, singulation, automatic inspection (AOI) and pick and pack in tape and reel.
Visit Nanium at www.nanium.com
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
