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Nanometric transistors take miniaturization into a new dimension

Nanometric transistors take miniaturization into a new dimension

Technology News |
By eeNews Europe



To achieve this result, the researchers at the Laboratoire d’Analyse et d’Architecture des Systèmes (LAAS-CNRS, Toulouse) and Institut d’Électronique, de Microélectronique et de Nanotechnologie (IEMN, CNRS / University of Lille / University of Valenciennes and Hainaut-Cambresis / Isen) developed a novel three-dimensional architecture consisting of a vertical nanowire array whose conductivity is controlled by a gate measuring 14 nm in length.

Published in Nanoscale, the findings open the way toward alternatives to the planar structures used in microprocessors and memory units. The use of 3D transistors could increase the power of microelectronic devices.

A team of researchers at the LAAS and IEMN has now built the first truly three-dimensional nanometric transistor. The device consists of a tight vertical nanowire array of about 200 nm in length linking two conductive surfaces. A chromium gate completely surrounds each nanowire and controls the flow of current, resulting in optimum transistor control for a system of this size. The gate is 14 nm in length, compared with 28 nm for the transistors in today’s chips, but its capacity to control the current in the transistor’s channel meets the requirements of contemporary microelectronics.

The architecture could lead to the development of microprocessors in which the transistors are stacked together. The number of transistors in a given space could thus be increased considerably, along with the performance capacity of microprocessors and memory units. Another advantage of these components is that they are relatively simple to manufacture and do not require high-resolution lithography. In addition, these 3D transistors could be easily integrated into the conventional microelectronic devices.

A patent has been filed for these transistors. The researchers now plan to continue their efforts to further reduce the size of the gate, which they believe could be made smaller than 10 nm while still providing satisfactory control over the transistor. In addition, the team is looking for industrial partners to help design the electronic devices of the future using the 3D architecture of these novel transistors.

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