Netezza selects Lattice device to integrate power management across three generations of board designs
As board designs become ever more complex, the traditional approach to power management using multiple discrete power management ICs from several different vendors is no longer viable from a board cost, reliability and time to market perspective. Instead, what is needed is an approach that integrates diverse power management functions into one power management IC.
“We chose the Power Manager device to help us deal with several board design and power management challenges,” said Ken Schwartz, Netezza Technology Director for hardware development. “For example, the proliferation of voltage regulators due to a distributed power architecture presented us with the challenge of replicating all the individual monitoring, control, and margining circuits. Power sequencing of complex ICs and memories require that almost every voltage rail be individually controlled. Programmability helps during debugging and stress testing. We also wanted finer resolution of margining under computer control, rather than using switches to connect and disconnect two margining resistor values. Further, we needed a power controller that can work with a mix of regulators from different vendors, and the Lattice Power Manager can do that".
“Other Power Manager features that appealed to us were the ability to use the integrated CPLD for small amounts of glue logic and programmable I/O; a way to compensate for voltage drops due to PCB characteristics or load variations; and the voltage feedback control, which could be effective with 24 A 1.0 V devices that have huge current variation potential. The PAC POWR 1220AT8 was able to solve all these design challenges for three generations of board designs,” Schwartz concluded.
Netezza used the Power Manager to integrate several functions, including:
- Voltage Monitoring + Over/Under Voltage Detection and Notification with much higher accuracy;
- Voltage Margining: Replaced a discrete switch and two resistors with a table-driven;
- DAC approach with up to 256 margin points;
- A general purpose I2C I/O register;
- Random glue logic.
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