Network synchronization system on a chip
The ACS9522T integrates a CPU, memory and six phase-lock loops (PLLs) needed to support IEEE 1588 packet-based synchronization as well as frequency synchronization via synchronous Ethernet or SONET/SDH. This closely coupled architecture delivers the industry’s best time alignment performance (better than 300 ns) by offering advanced features such as synchronous Ethernet / IEEE 1588 hybrid mode operation and network asymmetry correction.
It also supports different system synchronization architectures without loss of flexibility. The new multi-PLL architecture allows seamless integration of multiple local and network timing sources for enhanced system availability.
The device features a brand new GUI for rapid system configuration and prototyping, enabling an almost push-button process to convert the configuration into production system software. This is designed to significantly reduce costly reconfiguration and testing cycles and speed up time to market.
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