New 32bit microcontroller IP Core for low energy embedded applications
The APS3R core uses a 32-bit modern RISC architecture with sixteen 32-bit registers and a 5-7 stage pipeline. It is the second member of the Cortus microcontroller IP core family to be released in 2012 complementing the single precision floating point FPS6 core. It builds on experience with the earlier APS3 core but delivers improved computational performance. For more demanding embedded applications a dual core configuration is possible.
“Our first processor core, the APS3, has been the smallest available native 32-bit IP core since its release in early 2006,” says Michael Chapman, CEO and President of Cortus. “It has been in high volume production for almost four years in a wide range of applications ranging from SIM cards to Bluetooth LE. With the new APS3R we have found new ways to raise computational performance while keeping power consumption and silicon area small,” he said.
The CPU’s dynamic power is 11.6 µW/MHz with a standard 90 nm process and 16.8 µW/MHz for 130 nm (both UMC). The APS3R delivers 1.21 CoreMarks/MHz and 2.29 DMIPS/MHz computational performance.
The APS3R CPU core can be as small as 8,700 gates which is a size comparable to most 8-bit cores. APS3R is a native 32-bit core, optimised for use with C or C++, resulting in a software development process that is far more straightforward than that for 8- or 16-bit cores. With considerably more computation per clock cycle than with an 8-bit core, far fewer cycles are needed and therefore considerably less power is required. With superior code density, code memory is also smaller than with 8- or 16-bit cores thus reducing the silicon footprint of a subsystem.
The APS3R has been developed for applications requiring good computational performance but very low power. It is well suited to applications such as wireless communication, sensing, smart cards, SIM cards, touchscreen controllers and systems using energy harvesting.
For more computationally demanding applications an optional parallel hardware multiplier can improve the core performance to 1.92 CoreMarks/MHz. Further improvements are possible with a dual core APS3R configuration.
As a member of the Cortus family of processors, APS3R interfaces to all of Cortus’ peripherals including Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. It also shares the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead. Bridges to and from AHB-Lite and to APB ensure easy interfacing to other IP.
The APS toolchain and IDE (for C and C++) is available to licensees free of charge, and which can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium µC/OS and µCLinux.
www.cortus.com/aps3r.html
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