New 3D chip integrates computing, data storage to address data ‘superstorm’

Technology News | July 11, 2017

By Rich Pell

Unlike conventional silicon computing chips, which use separate chips for computing and data storage, the new design features a dense 3-D computer architecture that uses carbon nanotubes and resistive random-access memory (RRAM) cells that are built vertically over one another. According to the researchers, the design of the new chip will enable it to better process the coming “superstorm” of data from the increasingly ubiquitous embedded intelligence applications in everyday applications.

The nanotechnologies used in the chip are carbon nanotubes – sheets of 2D graphene formed into nanocylinders – and RRAM cells, a type of non-volatile memory that operates by changing the resistance of a solid dielectric material. The chip integrates over 1 million RRAM cells and 2 million carbon nanotube field-effect transistors (FETs), making it, say the researchers, “the most complex nanoelectronic system ever made with emerging nanotechnologies.”

The 3D architecture used in the new chip is not possible with existing silicon-based technology, says lead researcher Max Shulaker. “Circuits today are 2D, since building conventional silicon transistors involves extremely high temperatures of over 1,000 degrees Celsius. If you then build a second layer of silicon circuits on top, that high temperature will damage the bottom layer of circuits.”

Since carbon nanotube circuits and RRAM memory can be built at much lower temperatures – below 200°C – says Shulaker, “this means they can be built up in layers without harming the circuits beneath.”

The potential benefits for future computing systems, say the researchers, include faster and more energy efficient devices. Not only do the nanotechnologies used offer individual benefits, but the chip’s 3D integration addresses another key limitation of traditional devices – the interconnects within and between chips.

“The new 3-D computer architecture provides dense and fine-grained integration of computing and data storage, drastically overcoming the bottleneck from moving data between chips,” says Subhasish Mitra, professor of electrical engineering and computer science at Stanford. “As a result, the chip is able to store massive amounts of data and perform on-chip processing to transform a data deluge into useful information.”

In an additional demonstration of the new technology, the researchers also took advantage of the ability of carbon nanotubes to act as sensors by placing over 1 million carbon nanotube-based sensors on the top layer of the chip, which they used to detect ambient gases. According to researcher Shulaker, as a result of the chip’s layering of sensing, data storage, and computing, it was able to measure each of the sensors in parallel, and then write directly into its memory, generating huge bandwidth.

Another advantage of the technology, according to the researchers, is that it is compatible with today’s silicon infrastructure in terms of fabrication and design. “The fact that this strategy is both CMOS [complementary metal-oxide-semiconductor] compatible and viable for a variety of applications,” says says Ken Hansen, president and CEO of the Semiconductor Research Corporation, which supported the research, “suggests that it is a significant step in the continued advancement of Moore’s Law.”

The researchers are working to improve the underlying nanotechnologies, while continuing to explore the new 3D computer architecture. One plan is to work with chip maker Analog Devices on a version of the system that takes advantage of its ability to perform sensing and data processing on the same chip.

This, says Shulaker, could be used to create devices that detect signs of disease by sensing compounds in a patient’s breath. “The technology could not only improve traditional computing,” he says, “but also opens up a whole new range of applications that we can target. My students are now investigating how we can produce chips that do more than just computing.”

For more, see “Three-dimensional integration of nanotechnologies for computing and data storage on a single chip.”