The reference kit, along with the Cadence Library Characterizer technology, enable customers to re-characterize their standard cell libraries in-house, on their own schedule with the same characterization technology and setup used internally at TSMC, delivering better consistency.
Shrinking process geometries increase process variations and make creation of accurate noise, power and timing models for foundation IP complex given smaller time-to-market windows. The combination of TSMC’s Library Characterization Reference Kit and the Cadence Library Characterizer allows customers to speed their overall design schedule.
“Enabling our customers to re-characterize their standard cell library IP not only gives them more control over their schedule, it also gives them more control to address the timing, noise and power of their design,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. “By providing the Library Characterization Reference Kit online, we are giving our customers the tools needed to assure re-characterization that addresses their specific design challenges.”
The Cadence Library Characterizer technology enables re-characterization across process changes and additions to the IP library. The technology enables ultra-fast and accurate characterization of memory, standard cell libraries and other foundation IP, generating required models for SoC implementation. TSMC has made Cadence Library Characterizer scripts for standard cell libraries available for 40- and 28-nanometer process nodes.
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