MENU

New workflow allows automatic test bench generation for HDL verification

New workflow allows automatic test bench generation for HDL verification

By eeNews Europe



The new workflow includes MathWorks’ HDL Coder and HDL Verifier to automate the generation of test benches for HDL verification in both VHDL and Verilog and enable the rapid prototyping and verification of designs.

Microsemi customers can now integrate MATLAB and Simulink with Microsemi’s SmartFusion2 SoC FPGA and PolarFire FPGA development boards, allowing the stimulation of designs through FIL verification workflow using Microsemi’s development boards. The workflow also enables the analysis of the results in MATLAB and Simulink. The unified workflow also integrates Microsemi’s Libero SoC Design Suite with MATLAB and Simulink for design verification and provides FIL verification with Microsemi FPGA boards. This allows customers to catch bugs early in the design cycle. The collaboration provides an integrated workflow from algorithms to implementation.

More information

https://www.microsemi.com/product-directory/4194-partners

Related news

IAR Systems buys advanced security provider Secure Thingz​

Automotive tool accelerates trace timing analysis by 10x

IAR and DATA I/O partner to bring development and manufacturing closer

One Micro to buy another for $8.35 billion

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News

Share:

10s