Next-generation Bluetooth LE Audio codec IP
The new codec is designed to be compliant with the upcoming Bluetooth LC3 audio codec specification and is optimized to deliver high-quality audio and voice playback in battery-powered devices incorporating DesignWare® ARC® EM DSP and HS DSP processor IP.
The LC3 codec is an important feature of Bluetooth LE Audio, the soon-to-be-released next-generation audio standard defined by the Bluetooth Special Interest Group (SIG) that enables system-on-chip (SoC) designers to efficiently implement high-quality voice and audio streaming in a wide range of applications, including mobile, wearables, and home automation. The LC3 codec for ARC processors is based on an implementation by Fraunhofer IIS that is designed to meet Bluetooth SIG requirements. The new LC3 codec, running on ARC EM and HS DSP processors, allows designers to rapidly integrate a complete, pre-verified hardware and software solution for voice and speech processing into Bluetooth-enabled devices requiring minimal energy consumption.
“The rapid growth of wearable devices requiring high-quality Bluetooth audio streaming is driving the need for power-efficient processor IP with DSP capabilities that can meet intensive computation requirements of voice and audio applications. Those applications require an optimized codec providing state-of-the art voice and audio quality at minimum computational complexity. The LC3 codec is designed exactly like that,” said Manfred Lutzky, head of Audio for Communications at Fraunhofer IIS. “By porting the LC3 codec to the DSP-enhanced ARC processors, Synopsys is enabling customers to quickly implement LC3 codec functionality in their low-power SoCs.”
“The fact that the LC3 codec can provide very high-quality audio even at low bit rates makes it a key feature of the upcoming LE Audio standard,” said Mark Powell, chief executive officer of the Bluetooth Special Interest Group (SIG).
The 32-bit DesignWare ARC EM and HS DSP processors are based on the scalable ARCv2DSP Instruction Set Architecture (ISA) and integrate RISC and DSP capabilities for a flexible processing architecture. The ARC EM DSP processors offer ultra-low power and industry-leading performance efficiency while the multi-core-capable ARC HS DSP processors provide a unique combination of high-performance control and high-efficiency digital signal processing. All ARC processors are supported by the ARC MetaWare Development Toolkit, which includes a rich library of DSP functions to allow software engineers to rapidly implement algorithms from standard DSP building blocks. In addition, ARC processors and the LC3 codec can be combined with Synopsys’ Bluetooth 5.1-compliant DesignWare Bluetooth Low Energy IP to deliver power-efficient, high-quality wireless audio capability for smart IoT and other Bluetooth-enabled devices.
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