Niobium vias for multi-level superconducting quantum interconnect
Researchers in France have developed superconducting interconnect for cryogenically-cooled quantum chips built on silicon wafers.
The researchers at CEA-Leti have built a two-level superconducting backend-of-line (BEOL) using mainstream 200 mm silicon wafer technologies for quantum interconnect.
Scaling of solid-state quantum bits (qbits) requires more and more complex connectivity schemes within two- or three dimensional architectures, requiring superconducting interconnect appear essential to tackle the associated challenges of compactness, thermal management and signal dispersion. Heating from the interconnect can perturb the supercooled qbits and upset quantum coupling, which can be avoided with superconducting interconnect.
The BEOL is made with two niobium nitride (NbN) routing layers connected through planarized Nb-based plug vias, made using standard damascene techniques with a two step chemical mechanical polishing.
Wafer level parametric tests are used to assess the quality of the technology at room temperature and die-level low temperature electrical measurements in a cryostat are performed to evaluate the BEOL and more specifically the via superconducting properties.
The vias are characterized with a critical temperature ≥ 6.4 K, a critical magnetic field of ≈ 3.6 T and a critical current of 9.6 mA at 2 K and 0 T was evaluated for a 25×25 via array. Additionally, low temperature radio-frequency measurements at 9 K showed the stability of the via resistance up to a few GHz.
These first results demonstrate a strong potential to integrate this novel via technology within a superconducting BEOL, either overlayed onto spin qubits or as part of multi-layer wiring in multi-chip modules or interposers within solid-state qubit architectures, say the researchers.
Further RF measurements on test structures are ongoing to evaluate the cross-talk and the capacitive coupling between the routing levels as well as the impact of the vias on the inductance of two-level designed inductors. The via thickness is limited by the Nb PVD process, and this is driving investigation of other deposition techniques and materials for quantum chips.
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