NSITEXE chooses Imperas for RISC-V automotive processor

NSITEXE chooses Imperas for RISC-V automotive processor

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By Ally Winning

RISC-V is an open ISA that is flexible enough to allow many configurations and options for processor implementation and microarchitectural features. The vector instruction extensions have been developed to support the complex arithmetic operations that are required for applications involving linear algebra, such as AI and Machine Learning. In-depth testing and verification is needed to achieve the Automotive industry standard ASIL D safety requirement level of the ISO 26262 functional safety standard for vehicles.

Virtual Platforms that have been based on Imperas models and simulators provide early SoC architectural exploration to system developers wishing to map complex AI algorithms to new multiprocessor configurations. With RISC-V supporting both standard instruction extensions such as vectors, and user defined custom instructions, the Imperas models and analysis tools provide support for the flexibility and design freedoms for the front-end design flow. The hardware design verification (DV) team can then utilize the Imperas RISC-V reference model and verification suite to validate the design before tape-out. The Imperas verification suite includes a compliance validation test to ensure early compatibility with the growing ecosystem supporting RISC-V vectors.

“For the automotive market our customers expect the highest standards of quality and design assurance,” said Hideki Sugimoto, CTO of NSITEXE. “NSITEXE selected the Imperas Vector Extensions Compliance test cases and RISC-V Reference Model as a foundation for our simulation-based design verification (DV) plans.”

“Virtual platforms enable the essential early development of software well before RTL or silicon prototypes are available, which dramatically accelerates the time to market,” said Nobuyuki Ueyama, President of eSOL TRINITY Co., Ltd. “In addition, for the next generation of automotive AI designs, the early architectural exploration of the SoC helps validate the system design and becomes the reference model for RTL verification.”

“The RISC-V vector instruction extensions offer a broad set of parameterizable features, functions and options that can be fine-tuned for the target application,” said Simon Davidmann, CEO at Imperas Software Ltd. “Two of the most critical requirements of a professional DV plan are the reference model for functional verification and test suite for validation and ecosystem compliance. We are proud to support the engineering team at NSITEXE with the Imperas golden reference model for RISC-V, including vector extensions.”

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