NXP aims for microcontroller Nirvana
NXP is aiming to bring together its Kinetis and LPC microcontroller lines.
The four families in the 40nm MCX series are based around one ARM microcontroller core, the Cortex-M33, to provide scalable performance with common peripherals and a standard pinout. This will be based around the Xpresso development tools acquired with Code Red in 2013.
“We are expanding the scalability of the controllers and simplifying the design for customers and retaining the MCUXpresso development tools,” said CK Phua, product manager for microcontrollers at NXP. “This provides a migration path for Kinetis and LCP microcontrollers to make MCX the next great thing,” he said.
“The unification is coming from the combination of the LPC and Kinetis families. We left those two series running on their own and listened to all the feedback from customers so you don’t have to chose between the two. They are scalable all the way from the smallest memory to the highest 4MB flash,” he said.
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The MCX family also brings in the EdgeLock secure subsystem developed for the higher performance i.MX range for storing certificates and encryption keys for both end-to-end security and for production security.
“We do have another tool that couples with the secure enclave that provisions the chip so that it can’t be easily counterfeited,” he said. The chips will also be able to run the Zephyr, Azure and FreeRTOS real time operating systems with the cloud middleware.
The high end MCX N family has clock speeds from 150 to 250 MHz with a neural network processor unit (NPU), DSP and EdgeLock. The NPU was developed in-house and uses a vector engine that scales in performance from 32 ops/cycle to 2K ops/cycle.
The MCX A family runs from 48MHZ to 96MHz and is cost optimised with a low pin count.
The MCX W adds a 2.4GHz Bluetooth Low Energy (BLE) 5.3 wireless transceiver and runs from 32 to 150MHz. NXP is also planning a version that supports the 2.4GHz Matter protocol for the IoT, says Phua.
The MCX L is aimed at very low power, battery-backed designs, using techniques such as subthreshold switching, dynamic voltage adjustment and adaptive back bias (ABB) to reduce the active power consumption with speeds from 50 to 100MHz.
NXP has taped out a test chip on 40nm CMOS, says Phua, but is not yet using low power process such as fully depleted silicon on insulator (FD SOI process).
“We do have a series of microcontrollers on FDSOI but for the MCX we are not using FDSOI we are not relying on the process but on the design,” said Phua. “FDSOI will probably happen on the second generation.”
The first parts will sample by the end of the year on 40nm with more product details with products in H2 2023.
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