NXP changes naming for i.MX family

NXP changes naming for i.MX family

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The i.MX933 and 935 are the first to use ARM’s Ethos U65 neural processing unit   
By Nick Flaherty

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NXP has changed the naming conventions for its i.MX family of embedded processors.

The first members of the i.MX9 family are the i.MX933 and 935, which combine an ARM Cortex M55 real time core with two ARMv8 A55 processors and the first implementation of the ARM Ethos U65 neural engine. The 1GHz U65 is included in NXP’s ‘flex domain’ so that it can be used with the M55 for low power, ‘wake up word’ applications and with the A53 cores for higher performance processing such as image analysis or speed recognition.

The part, built on a 16nm FINFET process, is aimed at automotive, industrial and consumer applications with a 2D graphics engine and a wide range of I/Os for displays and camera sensors.

The naming will see cut down versions for the i.MX91 and i.MX92 families, rather than the ‘lite’ and ‘nano’ naming for the i.MX8 family. The 9 family will also include higher performance versions with more powerful M-class microcontroller cores and A-class processor cores  and a 3D processor for multimedia applications. This is expected to be the i.MX94 family, perhaps running up to the i.MX99.

“With multimedia being a key capability there will be different groupings of multimedia, 2D and 3D,” said Amanda McGregor, Senior Director, i.MX MPU Product Innovation for BL Edge Processing at NXP Semiconductors. “We will have 3D in the 9 families for multimedia and we are putting in the machine learning depending on the multimedia and the I/O and the ML will scale with that as well.”

“We haven’t announced the 91 and 92 yet which will have different packages for industrial and automotive and consumer packages,” she said. “The approach will be those devices below 93 with less performance and less I/O, 94 and above for performance and I/O richness, all with the same ML, security and energy efficiency. This is a great entry point for us, it complements the 8 family and we don’t have this level of performance in the previous devices,” she added. “We will start with the A55 up from the i.MX8m but there will be very different performance levels.”

There will be pin compatibility within families and between selected adjacent families and with the supporting power management (PMIC) devices, she says.

“We will have selective pin compatibility where it makes sense,” she said. “A 91 is not likely to be pin compatible with a 99  but within the family there will be pin compatibility and across select families. “e did that with the i.mx6 and i.mx8M and it is based on compatibility of the I/O.”

“When we build our PMICs we have the pin compatible packages in mind and the PMIC will launch at the same time with a power instrumented development kit with WiFi to pair with this for the alpha and beta launch,” she said. “It is similar to the PMIC in the 8M and 8 nano, not any more complex. The fewer voltage levels required [to power the device] the better but with the features on the part we do have a cost efficient PMIC pairing with the i.MX93.

The I/O on the 933 and 935 includes MIPI interfaces for cameras and displays, as well as CAN FD. While these are aimed at automotive designers, there are industrial and consumer designers using CAN for smart hubs she says.

“We have talked to consumer users that are using CAN in the home smart hubs, but they are not necessarily using the flexible data rate of FD,” she said. “We also have a parallel RGB interface that we did not have in the i.MX8m but now supports small displays. It muxes across the digital pins but the feature doesn’t take up a lot of space for IoT hub or gateway to connect sensors with a small QVGA display rather than an LVDS or MIPI panel and this ensures we are compatible with a many display standards as possible.”

Next: SRAM PUF in the i.MX9 family


The whole i.MX9 range adds the EdgeLock autonomous secure enclave with an SRAM physically unclonable function (PUF) from a third party supplier to provide the random number generation for the root of trust.

“The capabilities are similar to what we have in some of NXP devices that are already in market,” she said. “It’s a third party solution that relies on handler data to be stored in external memory and the SRAM PUF hardware key strength is 256 bits.”

NXP has previously used the SRAM PUF from Intrinsic-ID in Eindhoven, starting with the SmartMX in 2016.

“Since it is now part of NXP EdgeLock secure enclave, NXP will provide specific APIs to make PUF accessible to our customers,” she said.

EdgeLock includes Microsoft’s Pluton security software to provide connection to the Azure Sphere IoT cloud.

The U65 is programmed via NXP’s e.IQ development tool which allows TensorFlow Lite and ONNX neural frameworks to be implemented on the NPU core which has a capability of 256 MAC operations/cycle. The two A55 cores run up to 1.7GHz.

The 933 and 935 will sample in mid 2022 in an 11 x 11mm package with volume production in 2023 and will be part of NXPs’s longevity programme for long term support.

nxp.com/imx93

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