NXP said they would be used in the gateways that act as the car’s central communication node, coordinating all the CAN and other networks in the car and send data around the car and export it out to the cloud. The chip has 15 times the performance of NXP’s current range of networking chips while reducing power consumption. NXP said the S32G would be used in all new gateways that not only transfer data around the car but also take advantage of the data to support lane departure warnings and advanced driver assistance systems (ADAS)—as well as new services ranging from running diagnostics on the car to updating software from the cloud.
NXP said the S32G is based on lock-step Cortex-M7 microcontrollers and lock-step clusters of Cortex-A53 microprocessors that can support the ASIL-D standard. It also has dedicated network accelerators and encryption cores that send and secure data over CAN, Ethernet and other networks in the car, NXP said. Without acceleration, it would be impossible for the car to roll out new services with the deterministic networking needed by global OEMs.
“The central gateway is not only going to send data around the car anymore, it is also trying to run applications and services that can take advantage of all that data in cars and connect it to the cloud,” Brian Carlson, who leads product management for car networking processors at NXP, said ahead of the announcement at CES 2020. “But what we have seen is the need for more performance and networking to move all of that data around the car today.”
NXP, the world’s largest vendor of chips used in cars, has been struggling to chart its future in the looming age of autonomous cars. The company, hamstrung by Qualcomm’s failed bid to buy it, has been looking to repel rivals, including Intel and Nvidia, that have leapfrogged it in the development of artificial intelligence in cars. It is also fighting Infineon, Texas Instruments and Renesas in one of the big battlegrounds in the global chip business.
Qualcomm, the world’s largest vendor of chips used in smartphones, is also trying to swipe market share in cars. Qualcomm introduced the Snapdragon Ride computer at CES 2020 to ease the engineering challenges in autonomous cars, including lane departure controls and ADAS. Texas Instruments also introduced its latest line of ADAS SoCs, which it plans to start selling by the end of 2020, as well as another chip for network gateways.
NXP, which accounts for half of all the networking connections in new cars, is trying to stay ahead of the swelling communications load in cars. NXP said that around half of all cars on the road are connected to the cloud, which along with advanced driver assistance systems, or ADAS, is adding to the data deluge. That includes data about road conditions, stop signs, weather and other cars, all of which is today channeled through the central gateway.
The car’s communication network has long been dominated by the Controller Area Network or CAN bus. The CAN standard coordinates all the microcontrollers and electronic control units, or ECUs, that handle functions ranging from the powertrain and transmission to door locks and air conditioning. Local interconnect networks, or LINs, have also been slapped on cars over time to run communications for seat, window, mirror, and other body controls.
But as more sensors and other electronics are added to the car to enable blind spot alerts and automated emergency braking, the traditional networks have been falling behind. The FlexRay standard, which is currently the fastest at 10 Mbps, has also been struggling to slog through all the data from the cameras, radar and other sensors in the car to model its surroundings. The CAN standard has speeds of up to 1 Mbps. LIN supports up to 20 Kbps.
Car manufacturers are supplementing all the legacy networks in the car today by adding Ethernet with 100 Mbps and 1 Gbps speeds. The autonomous car of the future—which will add more cameras, radar and other sensors to model the surroundings in blinding blizzards and heavy downpours and react to dangers on the road ahead—will need Multi-Gigabit Ethernet, NXP said. New services are also worsening the communications crunch in the car.
For decades, manufacturers have added new features by adding more ECUs to the vehicle and connecting them to the gateway over CAN and LIN networks. More than 100 of these modules are currently crammed throughout the car to manage the windows, steering, signals and other domains—all of which are spewing out data. These devices are connected by vast lengths of cabling crammed in the dashboard, behind the doors, and under the floor.
But car manufacturers are now trying to condense all these isolated electronic devices into 10 to 20 supercomputers that are spread on the corners of the car and act as gateways, sharing data over Gigabit Ethernet networks. That would serve to cut down on all the costly cable harnesses in cars, NXP said. The microcontrollers in each box would be replaced by microprocessors that can be reprogrammed to roll out new features to the car over time.
“They want to move to a more central compute architecture,” Carlson said.
NXP is trying to bridge the gap between present and future electronic architectures in cars. The S32G is part of the company’s S32 platform, which is based on a common architecture so that customers can swap out software from one generation of cars to another and reuse up to 90% of research and development work. The point of the S32 platform is to curb costs and roll out safer, more “software upgradable” cars to the mass market faster than ever.
The chip incorporates 20 CAN interfaces, up from 8 in its current generation of networking chips for cars. The chip also has 4 Gigabit Ethernet interfaces, up from 100 Mbps Ethernet in its current range of gateway processors. It supports the highest standard of functional safety for electronics embedded in cars, ASIL-D, up from ASIL-C in its previous generation. NXP said it has started supplyingthe new networking chip to early customers, including Audi.
The chip also has network accelerators for Gigabit Ethernet as well as CAN, LIN, FlexRay and other legacy vehicle networking standards. Without acceleration, the chip would be bogged down by sending and securing data around the car, NXP said. The communications engine “offloads” most of that workload so that the Cortex-M and Cortex-A cores can be used for other services in the car, including over the air (OTA) updates and patches from the cloud.
The chip could also be used for running diagnostics on the engine, transmission or other parts. The chip could anticipate potential failures or parts that are wearing down, sending all that data to the cloud so that the manufacturer can send out replacement parts. Other services could share the location of potholes, debris or patches of invisible ice on the road ahead. “We are looking into how we can unlock more of the data in the car,” Carlson said.
The S32G is also ideal for integrating all the data from cameras, radar and other sensors around the car and feeding all that data to the ADAS safety controllers. The chip also has PCIe Gen 3 interfaces so that it can serve as the coprocessor to other chips carrying out the artificial intelligence chores in the car, NXP said. To guard against failures, the coprocessor has to corroborate the results from its counterpart before piloting the car out of trouble.
NXP said the S32G can also be used to secure the data shared around the car and swapped with the cloud. The chip incorporates a hardware security engine that serves as the root of trust, supporting secure boot to confirm that the system has not been infected by malicious code, and protecting against the pilfering of data in the car and the hijacking of the steering wheel or door locks. The encryption cores are barricaded from other blocks of the chip.
The Cortex-M7 cores can also serve as lock-step microcontrollers to add more redundancy. Each core in the pair runs through the same series of computations in parallel at the same time and watches out for malfunctions. The three pairs of cores can be compared to figure out whether faults or other errors have occurred in the duplicate core, NXP said. When the fault occurs, the other core takes control to reduce the chance of a single point of failure.
The Cortex-A53 cores can uniquely be used as lock-step microprocessors, NXP said. The cores are clustered in pairs so they can check each other for faults, boosting redundancy. The high-performance cores can be used in ADAS for alerting drivers to potential collisions or other dangers on the road ahead or autonomously steering the car out of danger, NXP said. The Cortex-A53 processors can also run independently if that redundancy is unnecessary.
“We don’t know anyone else offering that,” Carlson said.
This article was first published in Electronic Design – www.electronicdesign.com