NXP’s latest MPC5746R Power Architecture covered for debug
The high performance dual-core MPC5746R System-on-Chip (SoC), optimized for automotive engine/transmission control as well as industrial applications, offers users comprehensive features to ensure the highest level of functional safety (ASIL-D). Two Power Architecture z4 cores, running at up to 200 MHz, and the eTPU timer system meet the requirements of demanding applications. A broad selection of versions, regarding Flash sizes, core configurations and packaging options, is available for the MPC5746R.
With the UDE 4.6.1, chip internal debug functions of the MPC5746R can be completely utilized for test and debugging without any limitations. As a real multi-core debugger, the UDE can control the dual-core MPC5746R within one single debugger framework. The UDE 4.6.1’s multi-core run-control function enables an almost synchronous starting and stopping of both cores by utilizing the debug logic integrated on the chip. Additionally, multi-core breakpoints employed in shared code simplify debugging of complex applications. The breakpoint always takes effect regardless of which core is currently executing the particular code. Freely configurable perspectives within the user interface of the UDE 4.6.1 help developers maintain an overview in a multi-core application.
For system-level analyses, the UDE 4.6.1 provides trace-based tools, which utilize the Nexus Class 3 trace capabilities of the device. Thus, not only the program flow can be recorded for post-mortem analyses. The profiling information gained by these tools can be used for runtime optimization, for example. In addition, the UDE 4.6.1 provides the necessary code coverage to prove sufficient test coverage.
Visit PLS Programmierbare Logik & Systeme GmbH at www.pls-mc.com
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
